ARM: BeagleBoard-x15: Enable i2c5 clocks

[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c

diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 304ac1c17360c2242970fd3d53dae4b53cf25724..cd51fe7678be0182bbce06e046ce02f4e7023c99 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
        .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
        .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
        .cm_l3init_p1500_clkctrl = 0x4a009378,
+       .cm_l3init_sata_clkctrl = 0x4a009388,
        .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+       .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl = 0x4a009400,
@@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
        .control_status                         = 0x4A002134,
        .control_std_fuse_opp_vdd_mpu_2         = 0x4A0021B4,
        .control_phy_power_usb                  = 0x4A002370,
+       .control_phy_power_sata                 = 0x4A002374,
        .control_padconf_core_base              = 0x4A002800,
        .control_paconf_global                  = 0x4A002DA0,
        .control_paconf_mode                    = 0x4A002DA4,
@@ -373,6 +376,9 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_status                         = 0x4A002134,
+       .control_phy_power_usb                  = 0x4A002370,
+       .control_phy_power_sata                 = 0x4A002374,
+       .ctrl_core_sma_sw_0                     = 0x4A0023FC,
        .control_core_mac_id_0_lo               = 0x4A002514,
        .control_core_mac_id_0_hi               = 0x4A002518,
        .control_core_mac_id_1_lo               = 0x4A00251C,
@@ -428,11 +434,17 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_srcomp_code_latch              = 0x4A002E84,
        .control_ddr_control_ext_0              = 0x4A002E88,
        .control_padconf_core_base              = 0x4A003400,
+       .control_std_fuse_opp_vdd_mpu_2         = 0x4A003B20,
        .control_port_emif1_sdram_config        = 0x4AE0C110,
        .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
        .control_port_emif2_sdram_config        = 0x4AE0C118,
        .control_emif1_sdram_config_ext         = 0x4AE0C144,
        .control_emif2_sdram_config_ext         = 0x4AE0C148,
+       .control_wkup_ldovbb_mpu_voltage_ctrl   = 0x4AE0C158,
+       .control_std_fuse_die_id_0              = 0x4AE0C200,
+       .control_std_fuse_die_id_1              = 0x4AE0C208,
+       .control_std_fuse_die_id_2              = 0x4AE0C20C,
+       .control_std_fuse_die_id_3              = 0x4AE0C210,
        .control_padconf_mode                   = 0x4AE0C5A0,
        .control_xtal_oscillator                = 0x4AE0C5A4,
        .control_i2c_2                          = 0x4AE0C5A8,
@@ -441,11 +453,12 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
        .control_wkup_control_spare_r           = 0x4AE0C5B4,
        .control_wkup_control_spare_r_c0        = 0x4AE0C5B8,
        .control_srcomp_east_side_wkup          = 0x4AE0C5BC,
-       .control_efuse_1                        = 0x4AE0C5C0,
-       .control_efuse_2                        = 0x4AE0C5C4,
-       .control_efuse_3                        = 0x4AE0C5C8,
-       .control_efuse_4                        = 0x4AE0C5CC,
+       .control_efuse_1                        = 0x4AE0C5C8,
+       .control_efuse_2                        = 0x4AE0C5CC,
+       .control_efuse_3                        = 0x4AE0C5D0,
+       .control_efuse_4                        = 0x4AE0C5D4,
        .control_efuse_13                       = 0x4AE0C5F0,
+       .iodelay_config_base                    = 0x4844A000,
 };
 
 struct prcm_regs const omap5_es2_prcm = {
@@ -568,7 +581,7 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_div_m2_dpll_unipro = 0x4a0081d0,
        .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
        .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
-       .cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
+       .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
        .cm_coreaon_bandgap_clkctrl = 0x4a008648,
        .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
 
@@ -698,10 +711,11 @@ struct prcm_regs const omap5_es2_prcm = {
        .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
        .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
        .cm_l3init_p1500_clkctrl = 0x4a009678,
+       .cm_l3init_sata_clkctrl = 0x4a009688,
        .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
        .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
        .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
-       .cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
+       .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
 
        /* prm irqstatus regs */
        .prm_irqstatus_mpu_2 = 0x4ae06014,
@@ -793,7 +807,8 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_clkmode_dpll_dsp                    = 0x4a005234,
        .cm_shadow_freq_config1                 = 0x4a005260,
        .cm_clkmode_dpll_gmac                   = 0x4a0052a8,
-       .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688,
+       .cm_coreaon_usb_phy1_core_clkctrl       = 0x4a008640,
+       .cm_coreaon_usb_phy2_core_clkctrl       = 0x4a008688,
 
        /* cm1.mpu */
        .cm_mpu_mpu_clkctrl                     = 0x4a005320,
@@ -802,6 +817,13 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_dsp_clkstctrl                       = 0x4a005400,
        .cm_dsp_dsp_clkctrl                     = 0x4a005420,
 
+       /* cm IPU */
+       .cm_ipu_clkstctrl                       = 0x4a005540,
+       .cm_ipu_i2c5_clkctrl                    = 0x4a005578,
+
+       /* prm irqstatus regs */
+       .prm_irqstatus_mpu_2                    = 0x4ae06014,
+
        /* cm2.ckgen */
        .cm_clksel_usb_60mhz                    = 0x4a008104,
        .cm_clkmode_dpll_per                    = 0x4a008140,
@@ -891,9 +913,12 @@ struct prcm_regs const dra7xx_prcm = {
        .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
        .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
        .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
+       .cm_l3init_sata_clkctrl                 = 0x4a009388,
        .cm_gmac_clkstctrl                      = 0x4a0093c0,
        .cm_gmac_gmac_clkctrl                   = 0x4a0093d0,
        .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
+       .cm_l3init_ocp2scp3_clkctrl             = 0x4a0093e8,
+       .cm_l3init_usb_otg_ss1_clkctrl          = 0x4a0093f0,
 
        /* cm2.l4per */
        .cm_l4per_clkstctrl                     = 0x4a009700,
@@ -957,7 +982,11 @@ struct prcm_regs const dra7xx_prcm = {
        .prm_rstctrl                            = 0x4ae07d00,
        .prm_rstst                              = 0x4ae07d04,
        .prm_rsttime                            = 0x4ae07d08,
+       .prm_io_pmctrl                          = 0x4ae07d20,
        .prm_vc_val_bypass                      = 0x4ae07da0,
        .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
        .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,
+
+       .prm_abbldo_mpu_setup                   = 0x4AE07DDC,
+       .prm_abbldo_mpu_ctrl                    = 0x4AE07DE0,
 };