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ARM: DRA72-evm: Enable HW leveling
[people/ms/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e2ebab826232709a599d1d91e443f942ca7e660f..3022b9e06e22f4bb3888de1a1105e59e49a3b21d 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,20 +141,21 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851ab2,
        .sdram_config                   = 0x61851ab2,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400B,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
        .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -165,18 +166,44 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400B,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400B,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
+       .sdram_config_init              = 0x61862B32,
+       .sdram_config                   = 0x61862B32,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x0000514C,
+       .ref_ctrl_final                 = 0x0000144A,
+       .sdram_tim1                     = 0xD113781C,
+       .sdram_tim2                     = 0x305A7FDA,
+       .sdram_tim3                     = 0x409F86A8,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x5007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0024400D,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400D,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
        .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
        .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
@@ -267,6 +294,8 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                }
                break;
        case DRA722_ES1_0:
+               *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+               break;
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
@@ -392,52 +421,109 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
        0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-       0x00B000B0,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00800080,
-       0x00800080,
-       0x40010080,
+       0x10040100,
+       0x00910091,
+       0x00950095,
+       0x009B009B,
+       0x009E009E,
+       0x00980098,
+       0x00340034,
+       0x00350035,
+       0x00340034,
+       0x00310031,
+       0x00340034,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x00480048,
+       0x004A004A,
+       0x00520052,
+       0x00550055,
+       0x00500050,
+       0x00000000,
+       0x00600020,
+       0x40011080,
        0x08102040,
        0x0,
        0x0,
        0x0,
        0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
        0x0
 };
 
+/* Ext phy ctrl 1-35 regs */
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
-       0x00BB00BB,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
+       0x10040100,
+       0x00910091,
+       0x00950095,
+       0x009B009B,
+       0x009E009E,
+       0x00980098,
+       0x00330033,
+       0x00330033,
+       0x002F002F,
+       0x00320032,
+       0x00310031,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
+       0x00520052,
+       0x00520052,
+       0x00470047,
+       0x00490049,
+       0x00500050,
+       0x00000000,
+       0x00600020,
+       0x40011080,
+       0x08102040,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0
+};
+
+/* Ext phy ctrl 1-35 regs */
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+       0x10040100,
+       0x00A400A4,
+       0x00A900A9,
+       0x00B000B0,
+       0x00B000B0,
+       0x00A400A4,
+       0x00390039,
+       0x00320032,
+       0x00320032,
+       0x00320032,
+       0x00440044,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x007F007F,
+       0x004D004D,
+       0x00430043,
+       0x00560056,
+       0x00540054,
        0x00600060,
        0x0,
        0x00600020,
@@ -447,6 +533,11 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
        0x0,
        0x0,
        0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
        0x0
 };
 
@@ -458,7 +549,7 @@ const struct lpddr2_mr_regs mr_regs = {
        .mr16   = MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                                             const u32 **regs,
                                             u32 *size)
 {
@@ -478,7 +569,6 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                break;
        case DRA752_ES1_0:
        case DRA752_ES1_1:
-       case DRA722_ES1_0:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -489,6 +579,10 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
                }
                break;
+       case DRA722_ES1_0:
+               *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
+               *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
+               break;
        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
@@ -501,7 +595,7 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
        *regs = &mr_regs;
 }
 
-void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
 {
        u32 *ext_phy_ctrl_base = 0;
        u32 *emif_ext_phy_ctrl_base = 0;
@@ -540,6 +634,58 @@ void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
        }
 }
 
+static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
+{
+       struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+       u32 *emif_ext_phy_ctrl_base = 0;
+       u32 emif_nr;
+       const u32 *ext_phy_ctrl_const_regs;
+       u32 i, hw_leveling, size;
+
+       emif_nr = (base == EMIF1_BASE) ? 1 : 2;
+
+       hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+
+       emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
+
+       emif_get_ext_phy_ctrl_const_regs(emif_nr,
+                                        &ext_phy_ctrl_const_regs, &size);
+
+       writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
+       writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
+
+       if (!hw_leveling) {
+               /*
+                * Copy the predefined PHY register values
+                * in case of sw leveling
+                */
+               for (i = 1; i < 25; i++) {
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2]);
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2 + 1]);
+               }
+       } else {
+               /*
+                * Write the init value for HW levling to occur
+                */
+               for (i = 21; i < 35; i++) {
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2]);
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2 + 1]);
+               }
+       }
+}
+
+void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
+{
+       if (is_omap54xx())
+               do_ext_phy_settings_omap5(base, regs);
+       else
+               do_ext_phy_settings_dra7(base, regs);
+}
+
 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
        .max_freq       = 532000000,
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