board: icore-rqs: Fix mmc get env device

[people/ms/u-boot.git] / arch / arm / dts / imx6qdl-icore-rqs.dtsi

diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
index 2aaa6e4a87d47f2da51fe167863e73723b92193c..816cdce2f36c4150d8c15b3bcf48c1afad2f1602 100644 (file)
--- a/arch/arm/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi
@@ -43,11 +43,41 @@
 #include <dt-bindings/clock/imx6qdl-clock.h>
 
 / {
+       aliases {
+               mmc1 = &usdhc3;
+               mmc2 = &usdhc4;
+       };
+
        memory {
                reg = <0x10000000 0x80000000>;
        };
 };
 
+&fec {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_enet>;
+       phy-handle = <&eth_phy>;
+       phy-mode = "rgmii";
+       status = "okay";
+
+       mdio {
+               eth_phy: ethernet-phy {
+                       rxc-skew-ps = <1140>;
+                       txc-skew-ps = <1140>;
+                       txen-skew-ps = <600>;
+                       rxdv-skew-ps = <240>;
+                       rxd0-skew-ps = <420>;
+                       rxd1-skew-ps = <600>;
+                       rxd2-skew-ps = <420>;
+                       rxd3-skew-ps = <240>;
+                       txd0-skew-ps = <60>;
+                       txd1-skew-ps = <60>;
+                       txd2-skew-ps = <60>;
+                       txd3-skew-ps = <240>;
+               };
+       };
+};
+
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -75,6 +105,7 @@
 };
 
 &usdhc3 {
+       u-boot,dm-spl;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc3>;
        cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
@@ -82,7 +113,35 @@
        status = "okay";
 };
 
+&usdhc4 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_usdhc4>;
+       no-1-8-v;
+       status = "okay";
+};
+
 &iomuxc {
+       pinctrl_enet: enetgrp {
+               fsl,pins = <
+                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                       MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
+                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+               >;
+       };
+
        pinctrl_i2c1: i2c1grp {
                fsl,pins = <
                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@@ -112,6 +171,7 @@
        };
 
        pinctrl_usdhc3: usdhc3grp {
+               u-boot,dm-spl;
                fsl,pins = <
                        MX6QDL_PAD_SD3_CMD__SD3_CMD    0x17070
                        MX6QDL_PAD_SD3_CLK__SD3_CLK    0x10070
@@ -121,4 +181,19 @@
                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070
                >;
        };
+
+       pinctrl_usdhc4: usdhc4grp {
+               fsl,pins = <
+                       MX6QDL_PAD_SD4_CMD__SD4_CMD    0x17070
+                       MX6QDL_PAD_SD4_CLK__SD4_CLK    0x10070
+                       MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17070
+                       MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17070
+                       MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17070
+                       MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17070
+                       MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17070
+                       MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17070
+                       MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17070
+                       MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17070
+               >;
+       };
 };