/*
- * Device Tree Source for UniPhier PH1-LD11 SoC
+ * Device Tree Source for UniPhier LD11 SoC
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
- compatible = "socionext,ph1-ld11";
+ compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&mio_clk 3>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
+ <&mio_rst 12>;
};
usb1: usb@5a810100 {
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&mio_clk 4>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
+ <&mio_rst 13>;
};
usb2: usb@5a820100 {
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
- clocks = <&mio_clk 5>, <&mio_clk 6>;
+ clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
+ resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
+ <&mio_rst 14>;
};
mioctrl@5b3e0000 {