#include <asm/arch/hardware.h>
-#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
-/* cpu-id for AM33XX and TI81XX family */
+/* cpu-id for AM43XX AM33XX and TI81XX family */
+#define AM437X 0xB98C
#define AM335X 0xB944
#define TI81XX 0xB81E
#define DEVICE_ID (CTRL_BASE + 0x0600)
#define PRM_RSTCTRL_RESET 0x01
#define PRM_RSTST_WARM_RESET_MASK 0x232
-/*
- * Watchdog:
- * Using the prescaler, the OMAP watchdog could go for many
- * months before firing. These limits work without scaling,
- * with the 60 second default assumed by most tools and docs.
- */
-#define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
-#define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
-#define TIMER_MARGIN_MIN 1
-
-#define PTV 0 /* prescale */
-#define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
-#define WDT_WWPS_PEND_WCLR BIT(0)
-#define WDT_WWPS_PEND_WLDR BIT(2)
-#define WDT_WWPS_PEND_WTGR BIT(3)
-#define WDT_WWPS_PEND_WSPR BIT(4)
-
-#define WDT_WCLR_PRE BIT(5)
-#define WDT_WCLR_PTV_OFF 2
-
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
-
+#include <asm/ti-common/omap_wdt.h>
#ifndef CONFIG_AM43XX
/* Encapsulating core pll registers */
unsigned int timer0clkctrl; /* offset 0x10 */
unsigned int resv2[3];
unsigned int idlestdpllmpu; /* offset 0x20 */
- unsigned int resv3[2];
+ unsigned int sscdeltamstepdllmpu; /* off 0x24 */
+ unsigned int sscmodfreqdivdpllmpu; /* off 0x28 */
unsigned int clkseldpllmpu; /* offset 0x2c */
unsigned int resv4[1];
unsigned int idlestdpllddr; /* offset 0x34 */
struct cm_wkuppll {
unsigned int resv0[136];
unsigned int wkl4wkclkctrl; /* offset 0x220 */
- unsigned int resv1[55];
+ unsigned int resv1[7];
+ unsigned int usbphy0clkctrl; /* offset 0x240 */
+ unsigned int resv112;
+ unsigned int usbphy1clkctrl; /* offset 0x248 */
+ unsigned int resv113[45];
unsigned int wkclkstctrl; /* offset 0x300 */
unsigned int resv2[15];
unsigned int wkup_i2c0ctrl; /* offset 0x340 */
unsigned int l3clkstctrl; /* offset 0x00 */
unsigned int resv0[7];
unsigned int l3clkctrl; /* Offset 0x20 */
- unsigned int resv1[7];
+ unsigned int resv112[7];
unsigned int l3instrclkctrl; /* offset 0x40 */
unsigned int resv2[3];
unsigned int ocmcramclkctrl; /* offset 0x50 */
unsigned int qspiclkctrl; /* offset 0x258 */
unsigned int resv121;
unsigned int usb0clkctrl; /* offset 0x260 */
- unsigned int resv13[103];
+ unsigned int resv122;
+ unsigned int usb1clkctrl; /* offset 0x268 */
+ unsigned int resv13[101];
unsigned int l4lsclkstctrl; /* offset 0x400 */
unsigned int resv14[7];
unsigned int l4lsclkctrl; /* offset 0x420 */
unsigned int uart4clkctrl; /* offset 0x598 */
unsigned int resv35;
unsigned int uart5clkctrl; /* offset 0x5A0 */
- unsigned int resv36[87];
+ unsigned int resv36[5];
+ unsigned int usbphyocp2scp0clkctrl; /* offset 0x5B8 */
+ unsigned int resv361;
+ unsigned int usbphyocp2scp1clkctrl; /* offset 0x5C0 */
+ unsigned int resv3611[79];
unsigned int emifclkstctrl; /* offset 0x700 */
- unsigned int resv361[7];
+ unsigned int resv362[7];
unsigned int emifclkctrl; /* offset 0x720 */
unsigned int resv37[3];
unsigned int emiffwclkctrl; /* offset 0x730 */
unsigned int clkstctrl; /* offset 0x4 */
};
-/* Watchdog timer registers */
-struct wd_timer {
- unsigned int resv1[4];
- unsigned int wdtwdsc; /* offset 0x010 */
- unsigned int wdtwdst; /* offset 0x014 */
- unsigned int wdtwisr; /* offset 0x018 */
- unsigned int wdtwier; /* offset 0x01C */
- unsigned int wdtwwer; /* offset 0x020 */
- unsigned int wdtwclr; /* offset 0x024 */
- unsigned int wdtwcrr; /* offset 0x028 */
- unsigned int wdtwldr; /* offset 0x02C */
- unsigned int wdtwtgr; /* offset 0x030 */
- unsigned int wdtwwps; /* offset 0x034 */
- unsigned int resv2[3];
- unsigned int wdtwdly; /* offset 0x044 */
- unsigned int wdtwspr; /* offset 0x048 */
- unsigned int resv3[1];
- unsigned int wdtwqeoi; /* offset 0x050 */
- unsigned int wdtwqstar; /* offset 0x054 */
- unsigned int wdtwqsta; /* offset 0x058 */
- unsigned int wdtwqens; /* offset 0x05C */
- unsigned int wdtwqenc; /* offset 0x060 */
- unsigned int resv4[39];
- unsigned int wdt_unfr; /* offset 0x100 */
-};
-
/* Timer 32 bit registers */
struct gptimer {
unsigned int tidr; /* offset 0x00 */
#define OMAP_GPIO_SYSSTATUS 0x0114
#define OMAP_GPIO_IRQSTATUS1 0x002c
#define OMAP_GPIO_IRQSTATUS2 0x0030
+#define OMAP_GPIO_IRQSTATUS_SET_0 0x0034
+#define OMAP_GPIO_IRQSTATUS_SET_1 0x0038
#define OMAP_GPIO_CTRL 0x0130
#define OMAP_GPIO_OE 0x0134
#define OMAP_GPIO_DATAIN 0x0138
};
#define ECAP_CLK_EN BIT(0)
#define ECAP_CLK_STOP_REQ BIT(1)
+#define EPWM_CLK_EN BIT(8)
+#define EPWM_CLK_STOP_REQ BIT(9)
struct pwmss_ecap_regs {
unsigned int tsctr;
unsigned short ecctl2;
};
+struct pwmss_epwm_regs {
+ unsigned short tbctl;
+ unsigned short tbsts;
+ unsigned short tbphshr;
+ unsigned short tbphs;
+ unsigned short tbcnt;
+ unsigned short tbprd;
+ unsigned short res1;
+ unsigned short cmpctl;
+ unsigned short cmpahr;
+ unsigned short cmpa;
+ unsigned short cmpb;
+ unsigned short aqctla;
+ unsigned short aqctlb;
+ unsigned short aqsfrc;
+ unsigned short aqcsfrc;
+ unsigned short dbctl;
+ unsigned short dbred;
+ unsigned short dbfed;
+ unsigned short tzsel;
+ unsigned short tzctl;
+ unsigned short tzflg;
+ unsigned short tzclr;
+ unsigned short tzfrc;
+ unsigned short etsel;
+ unsigned short etps;
+ unsigned short etflg;
+ unsigned short etclr;
+ unsigned short etfrc;
+ unsigned short pcctl;
+ unsigned int res2[66];
+ unsigned short hrcnfg;
+};
+
/* Capture Control register 2 */
#define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
#define ECTRL2_MDSL_ECAP BIT(9)
projects / people / ms / u-boot.git / blobdiff