armv8: ls1088a: Add NXP LS1088A SoC support

[people/ms/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / config.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 79e94f9f2c4498b66dfa361e7b4664b139ab85cc..a7098be8463e7b6461b602d50ab02799008e452f 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -116,6 +116,67 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS             3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+#define CONFIG_SYS_PAGE_SIZE           0x10000
+
+#define        SRDS_MAX_LANES  4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE                              0x02200000
+#define TZPCR0SIZE_BASE                                (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE                        (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE                 (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE                 (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE                        (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE                 (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE                 (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE                        (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE                 (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE                 (TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE                      0x06000000
+#define GICR_BASE                      0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE                      0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE     ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+#define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE       0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00020000 /* Real size 128K */
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE              0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
@@ -218,7 +279,6 @@
 #define GICC_BASE              0x01420000
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
-
 #else
 #error SoC not defined
 #endif