#define ARCH_MXC
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
#define GPU_2D_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define OPENVG_ARB_END_ADDR 0x02207FFF
-#elif CONFIG_MX6SX
+#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00107FFF
#define GPU_ARB_BASE_ADDR 0x01800000
#define APBH_DMA_ARB_END_ADDR 0x0180BFFF
#define M4_BOOTROM_BASE_ADDR 0x007F8000
-#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
-#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
-#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
-
-#else
+#elif !defined(CONFIG_MX6SLL)
#define CAAM_ARB_BASE_ADDR 0x00100000
#define CAAM_ARB_END_ADDR 0x00103FFF
#define APBH_DMA_ARB_BASE_ADDR 0x00110000
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
/* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
#define GPV2_BASE_ADDR 0x00D00000
-#else
-#define GPV2_BASE_ADDR 0x00200000
-#endif
-
-#ifdef CONFIG_MX6SX
#define GPV3_BASE_ADDR 0x00E00000
#define GPV4_BASE_ADDR 0x00F00000
#define GPV5_BASE_ADDR 0x01000000
#define PCIE_ARB_END_ADDR 0x08FFFFFF
#else
+#define GPV2_BASE_ADDR 0x00200000
#define GPV3_BASE_ADDR 0x00300000
#define GPV4_BASE_ADDR 0x00800000
#define PCIE_ARB_BASE_ADDR 0x01000000
#define AIPS1_ARB_END_ADDR 0x020FFFFF
#define AIPS2_ARB_BASE_ADDR 0x02100000
#define AIPS2_ARB_END_ADDR 0x021FFFFF
-#ifdef CONFIG_MX6SX
+/* AIPS3 only on i.MX6SX */
#define AIPS3_ARB_BASE_ADDR 0x02200000
#define AIPS3_ARB_END_ADDR 0x022FFFFF
+#ifdef CONFIG_MX6SX
#define WEIM_ARB_BASE_ADDR 0x50000000
#define WEIM_ARB_END_ADDR 0x57FFFFFF
#define QSPI0_AMBA_BASE 0x60000000
#define QSPI0_AMBA_END 0x6FFFFFFF
#define QSPI1_AMBA_BASE 0x70000000
#define QSPI1_AMBA_END 0x7FFFFFFF
-#else
+#elif defined(CONFIG_MX6UL)
+#define WEIM_ARB_BASE_ADDR 0x50000000
+#define WEIM_ARB_END_ADDR 0x57FFFFFF
+#define QSPI0_AMBA_BASE 0x60000000
+#define QSPI0_AMBA_END 0x6FFFFFFF
+#elif !defined(CONFIG_MX6SLL)
#define SATA_ARB_BASE_ADDR 0x02200000
#define SATA_ARB_END_ADDR 0x02203FFF
#define OPENVG_ARB_BASE_ADDR 0x02204000
#define WEIM_ARB_END_ADDR 0x0FFFFFFF
#endif
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define MMDC0_ARB_BASE_ADDR 0x80000000
#define MMDC0_ARB_END_ADDR 0xFFFFFFFF
#define MMDC1_ARB_BASE_ADDR 0xC0000000
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
-#ifdef CONFIG_MX6SL
-#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
-#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
-#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
-#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
-#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
-#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
-#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
-#else
+
+#define MX6SL_UART5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SLL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6UL_UART7_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
+#define MX6SL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SLL_UART2_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6UL_UART8_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define MX6SL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SLL_UART3_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
+#define MX6SL_UART4_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
+
#ifndef CONFIG_MX6SX
#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
#endif
+#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE (ATZ1_BASE_ADDR + 0x24000)
#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
-#endif
#ifndef CONFIG_MX6SX
#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
+/* QOSC on i.MX6SLL */
+#define QOSC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
+#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
-#ifdef CONFIG_MX6SL
+#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
+#ifdef CONFIG_MX6SLL
+#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
+#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
+#define PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
+#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
+#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SL)
#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#elif CONFIG_MX6SX
+#elif defined(CONFIG_MX6SX)
#define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
#endif
+#define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+#define MX6SLL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
+
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
+#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
+
+#define CONFIG_SYS_FSL_SEC_OFFSET 0
+#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
+#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CONFIG_SYS_FSL_JR0_OFFSET)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
-#ifdef CONFIG_MX6SL
+/* i.MX6SL/SLL */
#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
-#elif CONFIG_MX6SX
-#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+#ifdef CONFIG_MX6UL
+#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
#else
-#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
+/* i.MX6SX */
+#define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#endif
+/* i.MX6DQ/SDL */
+#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
+#ifdef CONFIG_MX6SLL
+#define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
+#define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#endif
#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
+#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
#ifdef CONFIG_MX6SX
#define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#else
#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
#endif
#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_MX6UL
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+#elif defined(CONFIG_MX6SX)
#define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
-#else
-#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
-#endif
-#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
-#ifdef CONFIG_MX6SX
#define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#else
+#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#endif
+#define MX6UL_WDOG3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
+/* i.MX6SLL */
+#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#ifdef CONFIG_MX6SX
#define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
#define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
#define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
#define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
-#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
-#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
#define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
#define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
#define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
-#define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
#define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
#define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
#define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
#define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
#define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
+#elif defined(CONFIG_MX6ULL)
+#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
+#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
+#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
+#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
+#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
+#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
+#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
#endif
+/* Only for i.MX6SX */
+#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
+#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
+#define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
-#define CHIP_REV_1_0 0x10
-#define CHIP_REV_1_2 0x12
-#define CHIP_REV_1_5 0x15
-#ifndef CONFIG_MX6SX
+#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || \
+ defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
#define IRAM_SIZE 0x00040000
#else
#define IRAM_SIZE 0x00020000
#endif
#define FEC_QUIRK_ENET_MAC
+#include <asm/mach-imx/regs-lcdif.h>
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
+/* only for i.MX6SX/UL */
+#define WDOG3_BASE_ADDR ((is_mx6ul() ? \
+ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR))
+#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6SLL)) ? \
+ MX6SLL_LCDIF_BASE_ADDR : \
+ (is_cpu_type(MXC_CPU_MX6SL)) ? \
+ MX6SL_LCDIF_BASE_ADDR : \
+ ((is_cpu_type(MXC_CPU_MX6UL)) ? \
+ MX6UL_LCDIF1_BASE_ADDR : \
+ ((is_mx6ull()) ? \
+ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)))
+
+
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
#define SRC_SCR_CORE_1_RESET_OFFSET 14
#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[32]; /* Master Domain Assignment */
+ u32 reserved3[96];
+ u32 pdap[104]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[88];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[55];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
/* WEIM registers */
struct weim {
u32 cs0gcr1;
u32 gpr10;
};
+#define src_base ((struct src *)SRC_BASE_ADDR)
+
+#define SRC_SCR_M4_ENABLE_OFFSET 22
+#define SRC_SCR_M4_ENABLE_MASK (1 << 22)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4)
+
/* GPR1 bitfields */
+#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30)
+#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28)
+#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27)
+#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26)
+#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25)
+#define IOMUXC_GPR1_DPI_OFF BIT(24)
+#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22)
#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20)
+#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19)
+#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18)
+#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
+#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16)
+#define IOMUXC_GPR1_USB_EXP_MODE BIT(15)
+#define IOMUXC_GPR1_PCIE_INT BIT(14)
#define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
#define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
+#define IOMUXC_GPR1_GINT BIT(12)
+#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10)
+#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10)
+#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10)
+#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10)
+#define IOMUXC_GPR1_ACT_CS3 BIT(9)
+#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7)
+#define IOMUXC_GPR1_ACT_CS2 BIT(6)
+#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4)
+#define IOMUXC_GPR1_ACT_CS1 BIT(3)
+#define IOMUXC_GPR1_ADDRS0_OFFSET (1)
+#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1)
+#define IOMUXC_GPR1_ACT_CS0 BIT(0)
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+/* gpr12 bitfields */
+#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27)
+#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26)
+#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25)
+#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24)
+#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12)
+#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10)
+#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4)
struct iomuxc {
-#ifdef CONFIG_MX6SX
+#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
u8 reserved[0x4000];
#endif
u32 gpr[14];
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
+ defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL)
#define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \
ECSPI2_BASE_ADDR, \
u32 version;
u32 rsvd7[0xdb];
+ /* fuse banks */
struct fuse_bank {
u32 fuse_regs[0x20];
- } bank[16];
+ } bank[0];
};
struct fuse_bank0_regs {
u32 rsvd7[3];
};
-#ifdef CONFIG_MX6SX
+struct fuse_bank1_regs {
+ u32 mem0;
+ u32 rsvd0[3];
+ u32 mem1;
+ u32 rsvd1[3];
+ u32 mem2;
+ u32 rsvd2[3];
+ u32 mem3;
+ u32 rsvd3[3];
+ u32 mem4;
+ u32 rsvd4[3];
+ u32 ana0;
+ u32 rsvd5[3];
+ u32 ana1;
+ u32 rsvd6[3];
+ u32 ana2;
+ u32 rsvd7[3];
+};
+
struct fuse_bank4_regs {
u32 sjc_resp_low;
u32 rsvd0[3];
u32 sjc_resp_high;
u32 rsvd1[3];
- u32 mac_addr_low;
+ u32 mac_addr0;
u32 rsvd2[3];
- u32 mac_addr_high;
+ u32 mac_addr1;
u32 rsvd3[3];
- u32 mac_addr2;
+ u32 mac_addr2; /*For i.MX6SX and i.MX6UL*/
u32 rsvd4[7];
u32 gp1;
- u32 rsvd5[7];
+ u32 rsvd5[3];
+ u32 gp2;
+ u32 rsvd6[3];
};
-#else
-struct fuse_bank4_regs {
- u32 sjc_resp_low;
- u32 rsvd0[3];
- u32 sjc_resp_high;
- u32 rsvd1[3];
- u32 mac_addr_low;
- u32 rsvd2[3];
- u32 mac_addr_high;
- u32 rsvd3[0xb];
- u32 gp1;
- u32 rsvd4[3];
- u32 gp2;
- u32 rsvd5[3];
-};
-#endif
struct aipstz_regs {
u32 mprot0;
projects / people / ms / u-boot.git / blobdiff