MCU_CLK_DIV_SHIFT = 0,
MCU_CLK_DIV_MASK = GENMASK(4, 0),
+ /* CLKSEL_CON25 */
+ CLK_SARADC_DIV_CON_SHIFT = 8,
+ CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
+ CLK_SARADC_DIV_CON_WIDTH = 8,
+
/* CLKSEL43_CON */
+ GMAC_DIV_CON_SHIFT = 0x0,
+ GMAC_DIV_CON_MASK = GENMASK(4, 0),
+ GMAC_PLL_SHIFT = 6,
+ GMAC_PLL_MASK = GENMASK(7, 6),
+ GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
+ GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
GMAC_MUX_SEL_EXTCLK = BIT(8),
/* CLKSEL51_CON */