ARM: OMAP5: set mmc clock frequency to 192MHz

[people/ms/u-boot.git] / arch / arm / include / asm / omap_mmc.h

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 297e6a73802f27b156d699d72dfbc9ce829da5be..3d70148882cd8e530384a846a545c67bd16c3941 100644 (file)
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -28,15 +28,20 @@
 #include <mmc.h>
 
 struct hsmmc {
-#ifdef CONFIG_DM_MMC
-       unsigned char res0[0x100];
+#ifndef CONFIG_OMAP34XX
+       unsigned int hl_rev;
+       unsigned int hl_hwinfo;
+       unsigned int hl_sysconfig;
+       unsigned char res0[0xf4];
 #endif
        unsigned char res1[0x10];
        unsigned int sysconfig;         /* 0x10 */
        unsigned int sysstatus;         /* 0x14 */
        unsigned char res2[0x14];
        unsigned int con;               /* 0x2C */
-       unsigned char res3[0xD4];
+       unsigned int pwcnt;             /* 0x30 */
+       unsigned int dll;               /* 0x34 */
+       unsigned char res3[0xcc];
        unsigned int blk;               /* 0x104 */
        unsigned int arg;               /* 0x108 */
        unsigned int cmd;               /* 0x10C */
@@ -50,8 +55,13 @@ struct hsmmc {
        unsigned int sysctl;            /* 0x12C */
        unsigned int stat;              /* 0x130 */
        unsigned int ie;                /* 0x134 */
-       unsigned char res4[0x8];
+       unsigned char res4[0x4];
+       unsigned int ac12;              /* 0x13C */
        unsigned int capa;              /* 0x140 */
+       unsigned int capa2;             /* 0x144 */
+       unsigned char res5[0xc];
+       unsigned int admaes;            /* 0x154 */
+       unsigned int admasal;           /* 0x158 */
 };
 
 struct omap_hsmmc_plat {
@@ -59,11 +69,14 @@ struct omap_hsmmc_plat {
        struct hsmmc *base_addr;
        struct mmc mmc;
        bool cd_inverted;
+       u32 controller_flags;
+       const char *hw_rev;
 };
 
 /*
  * OMAP HS MMC Bit definitions
  */
+#define MADMA_EN                       (0x1 << 0)
 #define MMC_SOFTRESET                  (0x1 << 1)
 #define RESETDONE                      (0x1 << 0)
 #define NOOPENDRAIN                    (0x0 << 0)
@@ -80,12 +93,13 @@ struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH                 (0x0 << 8)
 #define RESERVED_MASK                  (0x3 << 9)
 #define CTPL_MMC_SD                    (0x0 << 11)
+#define DDR                            (0x1 << 19)
+#define DMA_MASTER                     (0x1 << 20)
 #define BLEN_512BYTESLEN               (0x200 << 0)
 #define NBLK_STPCNT                    (0x0 << 16)
-#define DE_DISABLE                     (0x0 << 0)
-#define BCE_DISABLE                    (0x0 << 1)
+#define DE_ENABLE                      (0x1 << 0)
 #define BCE_ENABLE                     (0x1 << 1)
-#define ACEN_DISABLE                   (0x0 << 2)
+#define ACEN_ENABLE                    (0x1 << 2)
 #define DDIR_OFFSET                    (4)
 #define DDIR_MASK                      (0x1 << 4)
 #define DDIR_WRITE                     (0x0 << 4)
@@ -117,15 +131,17 @@ struct omap_hsmmc_plat {
 #define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 #define SDBP_PWROFF                    (0x0 << 8)
 #define SDBP_PWRON                     (0x1 << 8)
+#define SDVS_MASK                      (0x7 << 9)
 #define SDVS_1V8                       (0x5 << 9)
 #define SDVS_3V0                       (0x6 << 9)
+#define SDVS_3V3                       (0x7 << 9)
+#define DMA_SELECT                     (0x2 << 3)
 #define ICE_MASK                       (0x1 << 0)
 #define ICE_STOP                       (0x0 << 0)
 #define ICS_MASK                       (0x1 << 1)
 #define ICS_NOTREADY                   (0x0 << 1)
 #define ICE_OSCILLATE                  (0x1 << 0)
 #define CEN_MASK                       (0x1 << 2)
-#define CEN_DISABLE                    (0x0 << 2)
 #define CEN_ENABLE                     (0x1 << 2)
 #define CLKD_OFFSET                    (6)
 #define CLKD_MASK                      (0x3FF << 6)
@@ -148,11 +164,24 @@ struct omap_hsmmc_plat {
 #define IE_DTO                         (0x01 << 20)
 #define IE_DCRC                                (0x01 << 21)
 #define IE_DEB                         (0x01 << 22)
+#define IE_ADMAE                       (0x01 << 25)
 #define IE_CERR                                (0x01 << 28)
 #define IE_BADA                                (0x01 << 29)
 
-#define VS30_3V0SUP                    (1 << 25)
-#define VS18_1V8SUP                    (1 << 26)
+#define VS33_3V3SUP                    BIT(24)
+#define VS30_3V0SUP                    BIT(25)
+#define VS18_1V8SUP                    BIT(26)
+
+#define AC12_ET                                BIT(22)
+#define AC12_V1V8_SIGEN                        BIT(19)
+#define AC12_SCLK_SEL                  BIT(23)
+#define AC12_UHSMC_MASK                        (7 << 16)
+#define AC12_UHSMC_DDR50               (4 << 16)
+#define AC12_UHSMC_SDR104              (3 << 16)
+#define AC12_UHSMC_SDR50               (2 << 16)
+#define AC12_UHSMC_SDR25               (1 << 16)
+#define AC12_UHSMC_SDR12               (0 << 16)
+#define AC12_UHSMC_RES                 (0x7 << 16)
 
 /* Driver definitions */
 #define MMCSD_SECTOR_SIZE              512
@@ -164,15 +193,43 @@ struct omap_hsmmc_plat {
 #define CLK_400KHZ                     1
 #define CLK_MISC                       2
 
+#define CLKD_MAX                       0x3FF   /* max clock divisor: 1023 */
+
 #define RSP_TYPE_NONE  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 #define MMC_CMD0       (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE    192 /* MHz */
+#else
 #define MMC_CLOCK_REFERENCE    96 /* MHz */
+#endif
+
+/* DLL */
+#define DLL_SWT                        BIT(20)
+#define DLL_FORCE_SR_C_SHIFT   13
+#define DLL_FORCE_SR_C_MASK    0x7f
+#define DLL_FORCE_VALUE                BIT(12)
+#define DLL_CALIB              BIT(1)
+
+#define MAX_PHASE_DELAY                0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50           BIT(13)
 
 #define mmc_reg_out(addr, mask, val)\
        writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
+               IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
+               IE_BRR | IE_BWR | IE_TC | IE_CC)
+
+#define CON_CLKEXTFREE         BIT(16)
+#define CON_PADEN              BIT(15)
+#define PSTATE_CLEV            BIT(24)
+#define PSTATE_DLEV            (0xF << 20)
+#define PSTATE_DLEV_DAT0       (0x1 << 20)
+
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
                int wp_gpio);