mmc: omap_hsmmc: add signal voltage selection support

[people/ms/u-boot.git] / arch / arm / include / asm / omap_mmc.h

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 507435a11f3f990a2784c92531c55ed4f6be1489..c6129c5348039323b5715e33d00d95de9e847b15 100644 (file)
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -39,7 +39,9 @@ struct hsmmc {
        unsigned int sysstatus;         /* 0x14 */
        unsigned char res2[0x14];
        unsigned int con;               /* 0x2C */
-       unsigned char res3[0xD4];
+       unsigned int pwcnt;             /* 0x30 */
+       unsigned int dll;               /* 0x34 */
+       unsigned char res3[0xcc];
        unsigned int blk;               /* 0x104 */
        unsigned int arg;               /* 0x108 */
        unsigned int cmd;               /* 0x10C */
@@ -56,7 +58,8 @@ struct hsmmc {
        unsigned char res4[0x4];
        unsigned int ac12;              /* 0x13C */
        unsigned int capa;              /* 0x140 */
-       unsigned char res5[0x10];
+       unsigned int capa2;             /* 0x144 */
+       unsigned char res5[0xc];
        unsigned int admaes;            /* 0x154 */
        unsigned int admasal;           /* 0x158 */
 };
@@ -67,6 +70,7 @@ struct omap_hsmmc_plat {
        struct mmc mmc;
        bool cd_inverted;
        u32 controller_flags;
+       const char *hw_rev;
 };
 
 /*
@@ -89,6 +93,7 @@ struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH                 (0x0 << 8)
 #define RESERVED_MASK                  (0x3 << 9)
 #define CTPL_MMC_SD                    (0x0 << 11)
+#define DDR                            (0x1 << 19)
 #define DMA_MASTER                     (0x1 << 20)
 #define BLEN_512BYTESLEN               (0x200 << 0)
 #define NBLK_STPCNT                    (0x0 << 16)
@@ -167,11 +172,9 @@ struct omap_hsmmc_plat {
 #define VS30_3V0SUP                    BIT(25)
 #define VS18_1V8SUP                    BIT(26)
 
-#define IOV_3V3                                3300000
-#define IOV_3V0                                3000000
-#define IOV_1V8                                1800000
-
 #define AC12_ET                                BIT(22)
+#define AC12_V1V8_SIGEN                        BIT(19)
+#define AC12_SCLK_SEL                  BIT(23)
 #define AC12_UHSMC_MASK                        (7 << 16)
 #define AC12_UHSMC_DDR50               (4 << 16)
 #define AC12_UHSMC_SDR104              (3 << 16)
@@ -198,9 +201,31 @@ struct omap_hsmmc_plat {
 /* Clock Configurations and Macros */
 #define MMC_CLOCK_REFERENCE    96 /* MHz */
 
+/* DLL */
+#define DLL_SWT                        BIT(20)
+#define DLL_FORCE_SR_C_SHIFT   13
+#define DLL_FORCE_SR_C_MASK    0x7f
+#define DLL_FORCE_VALUE                BIT(12)
+#define DLL_CALIB              BIT(1)
+
+#define MAX_PHASE_DELAY                0x7c
+
+/* CAPA2 */
+#define CAPA2_TSDR50           BIT(13)
+
 #define mmc_reg_out(addr, mask, val)\
        writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 
+#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\
+               IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\
+               IE_BRR | IE_BWR | IE_TC | IE_CC)
+
+#define CON_CLKEXTFREE         BIT(16)
+#define CON_PADEN              BIT(15)
+#define PSTATE_CLEV            BIT(24)
+#define PSTATE_DLEV            (0xF << 20)
+#define PSTATE_DLEV_DAT0       (0x1 << 20)
+
 int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio,
                int wp_gpio);