ARM: OMAP5: set mmc clock frequency to 192MHz

[people/ms/u-boot.git] / arch / arm / mach-omap2 / omap5 / hw_data.c

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index bb05e1920b962f8b0e4c2018f67a1d8459f309b7..7fc38368c996ba04ed2d4028e972817c4170f2af 100644 (file)
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -438,17 +438,17 @@ void enable_basic_clocks(void)
        setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
                        GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
-       /* Enable 96 MHz clock for MMC1 & MMC2 */
+       /* Enable 192 MHz clock for MMC1 & MMC2 */
        setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
        setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
                        HSMMC_CLKCTRL_CLKSEL_MASK);
 
        /* Set the correct clock dividers for mmc */
-       setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-                       HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-       setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-                       HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+       clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+                    HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+       clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+                    HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 
        /* Select 32KHz clock as the source of GPTIMER1 */
        setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,