#include <asm/arch/clock_manager.h>
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/scu.h>
+#include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+static struct scu_registers *scu_regs =
+ (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
+static struct nic301_registers *nic301_regs =
+ (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
+#endif
-#define MAIN_VCO_BASE ( \
- (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \
- CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \
- CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define PERI_VCO_BASE ( \
- (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \
- CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \
- CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \
- CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \
- )
-
-#define SDR_VCO_BASE ( \
- (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \
- CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \
- CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \
- (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \
- CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \
- )
+static const struct socfpga_system_manager *sysmgr_regs =
+ (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+
+u32 spl_boot_device(void)
+{
+ const u32 bsel = readl(&sysmgr_regs->bootinfo);
+
+ switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
+ case 0x1: /* FPGA (HPS2FPGA Bridge) */
+ return BOOT_DEVICE_RAM;
+ case 0x2: /* NAND Flash (1.8V) */
+ case 0x3: /* NAND Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(NAND), 0);
+ return BOOT_DEVICE_NAND;
+ case 0x4: /* SD/MMC External Transceiver (1.8V) */
+ case 0x5: /* SD/MMC Internal Transceiver (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
+ socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
+ return BOOT_DEVICE_MMC1;
+ case 0x6: /* QSPI Flash (1.8V) */
+ case 0x7: /* QSPI Flash (3.0V) */
+ socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
+ return BOOT_DEVICE_SPI;
+ default:
+ printf("Invalid boot device (bsel=%08x)!\n", bsel);
+ hang();
+ }
+}
+
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+static void socfpga_nic301_slave_ns(void)
+{
+ writel(0x1, &nic301_regs->lwhps2fpgaregs);
+ writel(0x1, &nic301_regs->hps2fpgaregs);
+ writel(0x1, &nic301_regs->acp);
+ writel(0x1, &nic301_regs->rom);
+ writel(0x1, &nic301_regs->ocram);
+ writel(0x1, &nic301_regs->sdrdata);
+}
void board_init_f(ulong dummy)
{
- struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+#endif
+ unsigned long sdram_size;
unsigned long reg;
+
/*
* First C code to run. Clear fake OCRAM ECC first as SBE
* and DBE might triggered during power on
memset(__bss_start, 0, __bss_end - __bss_start);
- /* Remap SDRAM to 0x0 */
- writel(0x1, &pl310->pl310_addr_filter_start);
+ socfpga_nic301_slave_ns();
- board_init_r(NULL, 0);
-}
+ /* Configure ARM MPU SNSAC register. */
+ setbits_le32(&scu_regs->sacr, 0xfff);
-u32 spl_boot_device(void)
-{
- return BOOT_DEVICE_RAM;
-}
+ /* Remap SDRAM to 0x0 */
+ writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
+ writel(0x1, &pl310->pl310_addr_filter_start);
-/*
- * Board initialization after bss clearance
- */
-void spl_board_init(void)
-{
- unsigned long sdram_size;
#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
- cm_config_t cm_default_cfg = {
- /* main group */
- MAIN_VCO_BASE,
- (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT <<
- CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT <<
- CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT <<
- CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT <<
- CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK <<
- CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK <<
- CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK <<
- CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET),
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) |
- (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP <<
- CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
-
- /* peripheral group */
- PERI_VCO_BASE,
- (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT <<
- CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT <<
- CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT <<
- CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT <<
- CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT <<
- CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET),
- (CONFIG_HPS_PERPLLGRP_DIV_USBCLK <<
- CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK <<
- CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK <<
- CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK <<
- CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET),
- (CONFIG_HPS_PERPLLGRP_SRC_QSPI <<
- CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_NAND <<
- CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) |
- (CONFIG_HPS_PERPLLGRP_SRC_SDMMC <<
- CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
-
- /* sdram pll group */
- SDR_VCO_BASE,
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT <<
- CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET),
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) |
- (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT <<
- CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
-
- };
-
debug("Freezing all I/O banks\n");
/* freeze all IO banks */
sys_mgr_frzctrl_freeze_req();
- socfpga_sdram_enable();
- socfpga_uart0_enable();
- socfpga_osc1timer_enable();
+ /* Put everything into reset but L4WD0. */
+ socfpga_per_reset_all();
+ /* Put FPGA bridges into reset too. */
+ socfpga_bridges_reset(1);
+
+ socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
+ socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
+ socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
timer_init();
debug("Reconfigure Clock Manager\n");
/* reconfigure the PLLs */
- cm_basic_init(&cm_default_cfg);
+ if (cm_basic_init(cm_default_cfg))
+ hang();
/* Enable bootrom to configure IOs. */
- sysmgr_enable_warmrstcfgio();
+ sysmgr_config_warmrstcfgio(1);
/* configure the IOCSR / IO buffer settings */
if (scan_mgr_configure_iocsr())
hang();
+ sysmgr_config_warmrstcfgio(0);
+
/* configure the pin muxing through system manager */
+ sysmgr_config_warmrstcfgio(1);
sysmgr_pinmux_init();
+ sysmgr_config_warmrstcfgio(0);
+
#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
- /* de-assert reset for peripherals and bridges based on handoff */
+ /* De-assert reset for peripherals and bridges based on handoff */
reset_deassert_peripherals_handoff();
+ socfpga_bridges_reset(0);
debug("Unfreezing/Thaw all I/O banks\n");
/* unfreeze / thaw all IO banks */
puts("SDRAM size check failed!\n");
hang();
}
+
+ socfpga_bridges_reset(1);
+
+ /* Configure simple malloc base pointer into RAM. */
+ gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
+}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void spl_board_init(void)
+{
+ /* configuring the clock based on handoff */
+ cm_basic_init(gd->fdt_blob);
+ WATCHDOG_RESET();
+
+ config_dedicated_pins(gd->fdt_blob);
+ WATCHDOG_RESET();
+
+ /* Release UART from reset */
+ socfpga_reset_uart(0);
+
+ /* enable console uart printing */
+ preloader_console_init();
+}
+
+void board_init_f(ulong dummy)
+{
+ /*
+ * Configure Clock Manager to use intosc clock instead external osc to
+ * ensure success watchdog operation. We do it as early as possible.
+ */
+ cm_use_intosc();
+
+ socfpga_watchdog_disable();
+
+ arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+ /* release osc1 watchdog timer 0 from reset */
+ socfpga_reset_deassert_osc1wd0();
+
+ /* reconfigure and enable the watchdog */
+ hw_watchdog_init();
+ WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
}
+#endif
projects / people / ms / u-boot.git / blobdiff