Convert CONFIG_ENV_IS_IN_FLASH to Kconfig

[people/ms/u-boot.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 097ad587c1cf643c769b7c071d27615b48578da9..b53206bf8ee78fb655c093e93a3ea9fc2ace8a26 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -20,6 +20,8 @@ config TARGET_QEMU_MIPS
        select SUPPORTS_CPU_MIPS32_R2
        select SUPPORTS_CPU_MIPS64_R1
        select SUPPORTS_CPU_MIPS64_R2
+       select ROM_EXCEPTION_VECTORS
+       imply ENV_IS_IN_FLASH
 
 config TARGET_MALTA
        bool "Support malta"
@@ -40,6 +42,8 @@ config TARGET_MALTA
        select SUPPORTS_CPU_MIPS64_R6
        select SWAP_IO_SPACE
        select MIPS_L1_CACHE_SHIFT_6
+       select ROM_EXCEPTION_VECTORS
+       imply ENV_IS_IN_FLASH
 
 config TARGET_VCT
        bool "Support vct"
@@ -47,6 +51,7 @@ config TARGET_VCT
        select SUPPORTS_CPU_MIPS32_R1
        select SUPPORTS_CPU_MIPS32_R2
        select SYS_MIPS_CACHE_INIT_RAM_LOAD
+       select ROM_EXCEPTION_VECTORS
 
 config TARGET_DBAU1X00
        bool "Support dbau1x00"
@@ -55,6 +60,7 @@ config TARGET_DBAU1X00
        select SUPPORTS_CPU_MIPS32_R1
        select SUPPORTS_CPU_MIPS32_R2
        select SYS_MIPS_CACHE_INIT_RAM_LOAD
+       select ROM_EXCEPTION_VECTORS
        select MIPS_TUNE_4KC
 
 config TARGET_PB1X00
@@ -63,6 +69,7 @@ config TARGET_PB1X00
        select SUPPORTS_CPU_MIPS32_R1
        select SUPPORTS_CPU_MIPS32_R2
        select SYS_MIPS_CACHE_INIT_RAM_LOAD
+       select ROM_EXCEPTION_VECTORS
        select MIPS_TUNE_4KC
 
 config ARCH_ATH79
@@ -70,6 +77,16 @@ config ARCH_ATH79
        select OF_CONTROL
        select DM
 
+config ARCH_BMIPS
+       bool "Support BMIPS SoCs"
+       select OF_CONTROL
+       select DM
+       select CLK
+       select CPU
+       select RAM
+       select SYSRESET
+       imply ENV_IS_NOWHERE
+
 config MACH_PIC32
        bool "Support Microchip PIC32"
        select OF_CONTROL
@@ -83,6 +100,7 @@ config TARGET_BOSTON
        select MIPS_CM
        select MIPS_L1_CACHE_SHIFT_6
        select MIPS_L2_CACHE
+       select OF_BOARD_SETUP
        select SUPPORTS_BIG_ENDIAN
        select SUPPORTS_LITTLE_ENDIAN
        select SUPPORTS_CPU_MIPS32_R1
@@ -91,6 +109,8 @@ config TARGET_BOSTON
        select SUPPORTS_CPU_MIPS64_R1
        select SUPPORTS_CPU_MIPS64_R2
        select SUPPORTS_CPU_MIPS64_R6
+       select ROM_EXCEPTION_VECTORS
+       imply ENV_IS_IN_FLASH
 
 config TARGET_XILFPGA
        bool "Support Imagination Xilfpga"
@@ -103,6 +123,7 @@ config TARGET_XILFPGA
        select SUPPORTS_CPU_MIPS32_R1
        select SUPPORTS_CPU_MIPS32_R2
        select MIPS_L1_CACHE_SHIFT_4
+       select ROM_EXCEPTION_VECTORS
        help
          This supports IMGTEC MIPSfpga platform
 
@@ -116,6 +137,7 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS
@@ -178,6 +200,7 @@ config CPU_MIPS64_R2
        bool "MIPS64 Release 2"
        depends on SUPPORTS_CPU_MIPS64_R2
        select 64BIT
+       imply ENV_IS_IN_FLASH
        help
          Choose this option to build a kernel for release 2 through 5 of the
          MIPS64 architecture.
@@ -192,6 +215,31 @@ config CPU_MIPS64_R6
 
 endchoice
 
+menu "General setup"
+
+config ROM_EXCEPTION_VECTORS
+       bool "Build U-Boot image with exception vectors"
+       help
+         Enable this to include exception vectors in the U-Boot image. This is
+         required if the U-Boot entry point is equal to the address of the
+         CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
+         U-Boot booted from parallel NOR flash).
+         Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
+         In that case the image size will be reduced by 0x500 bytes.
+
+config MIPS_CM_BASE
+       hex "MIPS CM GCR Base Address"
+       depends on MIPS_CM
+       default 0x16100000 if TARGET_BOSTON
+       default 0x1fbf8000
+       help
+         The physical base address at which to map the MIPS Coherence Manager
+         Global Configuration Registers (GCRs). This should be set such that
+         the GCRs occupy a region of the physical address space which is
+         otherwise unused, or at minimum that software doesn't need to access.
+
+endmenu
+
 menu "OS boot interface"
 
 config MIPS_BOOT_CMDLINE_LEGACY
@@ -281,6 +329,17 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
        bool
 
+config MIPS_INIT_STACK_IN_SRAM
+       bool
+       default n
+       help
+         Select this if the initial stack frame could be setup in SRAM.
+         Normally the initial stack frame is set up in DRAM which is often
+         only available after lowlevel_init. With this option the initial
+         stack frame and the early C environment is set up before
+         lowlevel_init. Thus lowlevel_init does not need to be implemented
+         in assembler.
+
 config SYS_DCACHE_SIZE
        int
        default 0
@@ -351,15 +410,6 @@ config MIPS_CM
          wish U-Boot to configure it or make use of it to retrieve system
          information such as cache configuration.
 
-config MIPS_CM_BASE
-       hex
-       default 0x1fbf8000
-       help
-         The physical base address at which to map the MIPS Coherence Manager
-         Global Configuration Registers (GCRs). This should be set such that
-         the GCRs occupy a region of the physical address space which is
-         otherwise unused, or at minimum that software doesn't need to access.
-
 endif
 
 endmenu