MIPS: Split I & D cache line size config

[people/ms/u-boot.git] / arch / mips / lib / cache_init.S

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 4bb9a17e749add16f0d709fea614a6bb27fe88eb..bc8ab27b58d92289088b8659d0ac224babdb6d46 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -101,14 +101,14 @@
 LEAF(mips_cache_reset)
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t2, CONFIG_SYS_ICACHE_SIZE
-       li      t8, CONFIG_SYS_CACHELINE_SIZE
+       li      t8, CONFIG_SYS_ICACHE_LINE_SIZE
 #else
        l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
 #ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t3, CONFIG_SYS_DCACHE_SIZE
-       li      t9, CONFIG_SYS_CACHELINE_SIZE
+       li      t9, CONFIG_SYS_DCACHE_LINE_SIZE
 #else
        l1_info t3, t9, MIPS_CONF1_DA_SHF
 #endif