Add GPL-2.0+ SPDX-License-Identifier to source files

[people/ms/u-boot.git] / arch / powerpc / cpu / mpc86xx / interrupts.c

diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c
index d8ad6d30d6fa096b4ef7b97789beece84b128488..765aab5cfb7556f59fd56a77a3130ac0fb6391be 100644 (file)
--- a/arch/powerpc/cpu/mpc86xx/interrupts.c
+++ b/arch/powerpc/cpu/mpc86xx/interrupts.c
@@ -12,68 +12,68 @@
  * Jeff Brown
  * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <mpc86xx.h>
 #include <command.h>
 #include <asm/processor.h>
+#ifdef CONFIG_POST
+#include <post.h>
+#endif
 
 int interrupt_init_cpu(unsigned long *decrementer_count)
 {
        volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
        volatile ccsr_pic_t *pic = &immr->im_pic;
 
+#ifdef CONFIG_POST
+       /*
+        * The POST word is stored in the PIC's TFRR register which gets
+        * cleared when the PIC is reset.  Save it off so we can restore it
+        * later.
+        */
+       ulong post_word = post_word_load();
+#endif
+
        pic->gcr = MPC86xx_PICGCR_RST;
        while (pic->gcr & MPC86xx_PICGCR_RST)
                ;
        pic->gcr = MPC86xx_PICGCR_MODE;
 
        *decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
-       debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n",
+       debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %ld\n",
              (get_tbclk() / 1000000),
              *decrementer_count);
 
 #ifdef CONFIG_INTERRUPTS
 
        pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */
-       debug("iivpr1@%x = %x\n", &pic->iivpr1, pic->iivpr1);
+       debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1);
 
        pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
-       debug("iivpr2@%x = %x\n", &pic->iivpr2, pic->iivpr2);
+       debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2);
 
        pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
-       debug("iivpr3@%x = %x\n", &pic->iivpr3, pic->iivpr3);
+       debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3);
 
 #if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1)
        pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */
-       debug("iivpr8@%x = %x\n", &pic->iivpr8, pic->iivpr8);
+       debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8);
 #endif
 #if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
        pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */
-       debug("iivpr9@%x = %x\n", &pic->iivpr9, pic->iivpr9);
+       debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9);
 #endif
 
        pic->ctpr = 0;  /* 40080 clear current task priority register */
 #endif
 
+#ifdef CONFIG_POST
+       post_word_store(post_word);
+#endif
+
        return 0;
 }