drivers, block: remove sil680 driver

[people/ms/u-boot.git] / arch / powerpc / cpu / ppc4xx / 4xx_pcie.c

diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
index a87e93b80c112a7191dbdf709779ca8642258e7e..a616365aa57b1177ce84f7b7ec8a8c4a01912568 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
+++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c
@@ -5,19 +5,7 @@
  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
  * Roland Dreier <rolandd@cisco.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* define DEBUG for debugging output (obviously ;-)) */
@@ -30,7 +18,7 @@
 #include <asm/ppc4xx.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 
 #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) ||        \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
@@ -227,7 +215,6 @@ static void pcie_dmer_enable(void)
 static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
        int offset, int len, u32 *val) {
 
-       u8 *address;
        *val = 0;
 
        if (validate_endpoint(hose))
@@ -255,7 +242,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
                ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
                return 0;
 
-       address = pcie_get_base(hose, devfn);
+       pcie_get_base(hose, devfn);
        offset += devfn << 4;
 
        /*
@@ -287,8 +274,6 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
 static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
        int offset, int len, u32 val) {
 
-       u8 *address;
-
        if (validate_endpoint(hose))
                return 0;               /* No upstream config access */
 
@@ -307,7 +292,7 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
                ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
                return 0;
 
-       address = pcie_get_base(hose, devfn);
+       pcie_get_base(hose, devfn);
        offset += devfn << 4;
 
        /*
@@ -1063,7 +1048,6 @@ int ppc4xx_init_pcie_endport(int port)
 void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
 {
        volatile void *mbase = NULL;
-       volatile void *rmbase = NULL;
 
        pci_set_ops(hose,
                    pcie_read_config_byte,
@@ -1076,18 +1060,15 @@ void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port)
        switch (port) {
        case 0:
                mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE;
-               rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE;
                hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE;
                break;
        case 1:
                mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE;
-               rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE;
                hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE;
                break;
 #if CONFIG_SYS_PCIE_NR_PORTS > 2
        case 2:
                mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE;
-               rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE;
                hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE;
                break;
 #endif