/* 3Com Ethernet PCI definitions*/
-// #define PCI_VENDOR_ID_3COM 0x10B7
+/* #define PCI_VENDOR_ID_3COM 0x10B7 */
#define PCI_DEVICE_ID_3COM_3C905C 0x9200
/* 3Com Commands, top 5 bits are command and bottom 11 bits are parameters */
-#define TotalReset (0<<11)
+#define TotalReset (0<<11)
#define SelectWindow (1<<11)
#define StartCoax (2<<11)
-#define RxDisable (3<<11)
-#define RxEnable (4<<11)
+#define RxDisable (3<<11)
+#define RxEnable (4<<11)
#define RxReset (5<<11)
-#define UpStall (6<<11)
+#define UpStall (6<<11)
#define UpUnstall (6<<11)+1
-#define DownStall (6<<11)+2
+#define DownStall (6<<11)+2
#define DownUnstall (6<<11)+3
#define RxDiscard (8<<11)
#define TxEnable (9<<11)
-#define TxDisable (10<<11)
+#define TxDisable (10<<11)
#define TxReset (11<<11)
-#define FakeIntr (12<<11)
-#define AckIntr (13<<11)
+#define FakeIntr (12<<11)
+#define AckIntr (13<<11)
#define SetIntrEnb (14<<11)
-#define SetStatusEnb (15<<11)
+#define SetStatusEnb (15<<11)
#define SetRxFilter (16<<11)
#define SetRxThreshold (17<<11)
-#define SetTxThreshold (18<<11)
+#define SetTxThreshold (18<<11)
#define SetTxStart (19<<11)
#define StartDMAUp (20<<11)
#define StartDMADown (20<<11)+1
#define StatsEnable (21<<11)
-#define StatsDisable (22<<11)
+#define StatsDisable (22<<11)
#define StopCoax (23<<11)
#define SetFilterBit (25<<11)
/* The SetRxFilter command accepts the following classes */
-#define RxStation 1
-#define RxMulticast 2
-#define RxBroadcast 4
+#define RxStation 1
+#define RxMulticast 2
+#define RxBroadcast 4
#define RxProm 8
/* 3Com status word defnitions */
#define HostError 0x0002
#define TxComplete 0x0004
#define TxAvailable 0x0008
-#define RxComplete 0x0010
+#define RxComplete 0x0010
#define RxEarly 0x0020
#define IntReq 0x0040
#define StatsFull 0x0080
#define DMADone (1<<8)
-#define DownComplete (1<<9)
+#define DownComplete (1<<9)
#define UpComplete (1<<10)
#define DMAInProgress (1<<11) /* DMA controller is still busy.*/
#define CmdInProgress (1<<12) /* EL3_CMD is still busy.*/
/* EEPROM locations. */
-#define PhysAddr01 0
+#define PhysAddr01 0
#define PhysAddr23 1
-#define PhysAddr45 2
+#define PhysAddr45 2
#define ModelID 3
-#define EtherLink3ID 7
-#define IFXcvrIO 8
+#define EtherLink3ID 7
+#define IFXcvrIO 8
#define IRQLine 9
-#define NodeAddr01 10
-#define NodeAddr23 11
+#define NodeAddr01 10
+#define NodeAddr23 11
#define NodeAddr45 12
-#define DriverTune 13
+#define DriverTune 13
#define Checksum 15
/* Register window 1 offsets, the window used in normal operation */
-#define TX_FIFO 0x10
-#define RX_FIFO 0x10
+#define TX_FIFO 0x10
+#define RX_FIFO 0x10
#define RxErrors 0x14
-#define RxStatus 0x18
-#define Timer 0x1A
+#define RxStatus 0x18
+#define Timer 0x1A
#define TxStatus 0x1B
#define TxFree 0x1C /* Remaining free bytes in Tx buffer. */
/* Register Window 2 */
-
+
#define Wn2_ResetOptions 12
/* Register Window 3: MAC/config bits */
#define Wn3_Options 8
#define BFEXT(value, offset, bitcount) \
- ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
+ ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
#define BFINS(lhs, rhs, offset, bitcount) \
- (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
- (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
+ (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
+ (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
#define RAM_SIZE(v) BFEXT(v, 0, 3)
#define RAM_WIDTH(v) BFEXT(v, 3, 1)
#define AUTOSELECT(v) BFEXT(v, 24, 1)
/* Register Window 4: Xcvr/media bits */
-
+
#define Wn4_FIFODiag 4
#define Wn4_NetDiag 6
#define Wn4_PhysicalMgmt 8
#define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
struct rx_desc_3com {
- u32 next; /* Last entry points to 0 */
- u32 status; /* FSH -> Frame Start Header */
- u32 addr; /* Up to 63 addr/len pairs possible */
- u32 length; /* Set LAST_FRAG to indicate last pair */
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* FSH -> Frame Start Header */
+ u32 addr; /* Up to 63 addr/len pairs possible */
+ u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Values for the Rx status entry. */
#define RxDComplete 0x00008000
#define RxDError 0x4000
-#define IPChksumErr (1<<25)
-#define TCPChksumErr (1<<26)
+#define IPChksumErr (1<<25)
+#define TCPChksumErr (1<<26)
#define UDPChksumErr (1<<27)
-#define IPChksumValid (1<<29)
+#define IPChksumValid (1<<29)
#define TCPChksumValid (1<<30)
#define UDPChksumValid (1<<31)
struct tx_desc_3com {
- u32 next; /* Last entry points to 0 */
- u32 status; /* bits 0:12 length, others see below */
- u32 addr;
- u32 length;
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* bits 0:12 length, others see below */
+ u32 addr;
+ u32 length;
};
/* Values for the Tx status entry. */
/* XCVR Types */
#define XCVR_10baseT 0
-#define XCVR_AUI 1
+#define XCVR_AUI 1
#define XCVR_10baseTOnly 2
-#define XCVR_10base2 3
+#define XCVR_10base2 3
#define XCVR_100baseTx 4
#define XCVR_100baseFx 5
#define XCVR_MII 6
#define XCVR_Default 10 /* I don't think this is correct -> should have been 0x10 if Auto Negotiate */
struct descriptor { /* A generic descriptor. */
- u32 next; /* Last entry points to 0 */
- u32 status; /* FSH -> Frame Start Header */
- u32 addr; /* Up to 63 addr/len pairs possible */
- u32 length; /* Set LAST_FRAG to indicate last pair */
+ u32 next; /* Last entry points to 0 */
+ u32 status; /* FSH -> Frame Start Header */
+ u32 addr; /* Up to 63 addr/len pairs possible */
+ u32 length; /* Set LAST_FRAG to indicate last pair */
};
/* Misc. definitions */
static inline void ETH_CMD(struct eth_device* dev, int command)
{
- *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
+ *(volatile u16 *)io_to_phys(EL3_CMD + dev->iobase) = cpu_to_le16(command);
__asm volatile ("eieio");
}
static int issue_and_wait(struct eth_device* dev, int command)
{
- int i, status;
+ int i, status;
ETH_CMD(dev, command);
- for (i = 0; i < 2000; i++) {
- status = ETH_STATUS(dev);
- //printf ("Issue: status 0x%4x.\n", status);
+ for (i = 0; i < 2000; i++) {
+ status = ETH_STATUS(dev);
+ /*printf ("Issue: status 0x%4x.\n", status); */
if (!(status & CmdInProgress))
- return 1;
- }
-
- /* OK, that didn't work. Do it the slow way. One second */
- for (i = 0; i < 100000; i++) {
- status = ETH_STATUS(dev);
- //printf ("Issue: status 0x%4x.\n", status);
- return 1;
- udelay(10);
- }
- PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
+ return 1;
+ }
+
+ /* OK, that didn't work. Do it the slow way. One second */
+ for (i = 0; i < 100000; i++) {
+ status = ETH_STATUS(dev);
+ /*printf ("Issue: status 0x%4x.\n", status); */
+ return 1;
+ udelay(10);
+ }
+ PRINTF("Ethernet command: 0x%4x did not complete! Status: 0x%4x\n", command, ETH_STATUS(dev) );
return 0;
}
EL3WINDOW(dev, 1);
- // Wait for Auto negotiation to complete
+ /* Wait for Auto negotiation to complete */
for (i = 0; i <= 1000; i++)
{
if (ETH_INW(dev, 2) & 0x04)
return 0;
}
}
-
return 1;
int eth_3com_initialize(bd_t *bis)
{
- u32 eth_iobase = 0, status;
- int card_number = 0, ret;
- struct eth_device* dev;
- pci_dev_t devno;
+ u32 eth_iobase = 0, status;
+ int card_number = 0, ret;
+ struct eth_device* dev;
+ pci_dev_t devno;
char *s;
s = getenv("3com_base");
}
ret = pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, ð_iobase);
- eth_iobase &= ~0xf;
+ eth_iobase &= ~0xf;
PRINTF("eth: 3Com Found at Address: 0x%x\n", eth_iobase);
-
+
pci_write_config_dword(devno, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled */
goto Done;
}
- dev = (struct eth_device*) malloc(sizeof(*dev)); //struct eth_device));
+ dev = (struct eth_device*) malloc(sizeof(*dev)); /*struct eth_device)); */
- sprintf(dev->name, "3Com 3c920c#%d", card_number);
- dev->iobase = eth_iobase;
- dev->priv = (void*) devno;
- dev->init = eth_3com_init;
- dev->halt = eth_3com_halt;
- dev->send = eth_3com_send;
- dev->recv = eth_3com_recv;
+ sprintf(dev->name, "3Com 3c920c#%d", card_number);
+ dev->iobase = eth_iobase;
+ dev->priv = (void*) devno;
+ dev->init = eth_3com_init;
+ dev->halt = eth_3com_halt;
+ dev->send = eth_3com_send;
+ dev->recv = eth_3com_recv;
- eth_register(dev);
+ eth_register(dev);
/* { */
/* char interrupt; */
/* devno = pci_find_device(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C905C, 0); */
/* pci_read_config_byte(devno, PCI_INTERRUPT_LINE, &interrupt); */
-
+
/* printf("Installing eth0 interrupt handler to %d\n", interrupt); */
/* irq_install_handler(interrupt, eth_interrupt, dev); */
/* } */
- card_number++;
+ card_number++;
/* Set the latency timer for value */
s = getenv("3com_latency");
PRINTF ("Cannot allocate memory for RX_RING.....\n");
goto Done;
}
-
+
if (!(tx_ring = memalign(sizeof(struct tx_desc_3com) * NUM_TX_DESC, 16)))
{
PRINTF ("Cannot allocate memory for TX_RING.....\n");
goto Done;
}
-
+
Done:
return status;
}
struct descriptor *ias_cmd;
/* Determine what type of network the machine is connected to */
- /* presently drops the connect to 10Mbps */
+ /* presently drops the connect to 10Mbps */
if (!auto_negotiate(dev))
{
goto Done;
}
- issue_and_wait(dev, TxReset);
- issue_and_wait(dev, RxReset|0x04);
+ issue_and_wait(dev, TxReset);
+ issue_and_wait(dev, RxReset|0x04);
- /* Switch to register set 7 for normal use. */
- EL3WINDOW(dev, 7);
+ /* Switch to register set 7 for normal use. */
+ EL3WINDOW(dev, 7);
/* Initialize Rx and Tx rings */
init_rx_ring(dev);
purge_tx_ring(dev);
- ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
+ ETH_CMD(dev, SetRxFilter | RxStation | RxBroadcast | RxProm);
- issue_and_wait(dev,SetTxStart|0x07ff);
+ issue_and_wait(dev,SetTxStart|0x07ff);
- /* Below sets which indication bits to be seen. */
+ /* Below sets which indication bits to be seen. */
- status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
- ETH_CMD(dev, status_enable);
+ status_enable = SetStatusEnb | HostError | DownComplete | UpComplete | (1<<6);
+ ETH_CMD(dev, status_enable);
/* Below sets no bits are to cause an interrupt since this is just polling */
- intr_enable = SetIntrEnb;
-// intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6);
- ETH_CMD(dev, intr_enable);
+ intr_enable = SetIntrEnb;
+/* intr_enable = SetIntrEnb | (1<<9) | (1<<10) | (1<<6); */
+ ETH_CMD(dev, intr_enable);
ETH_OUTB(dev, 127, UpPoll);
- /* Ack all pending events, and set active indicator mask */
+ /* Ack all pending events, and set active indicator mask */
- ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
- ETH_CMD(dev, intr_enable);
+ ETH_CMD(dev, AckIntr | IntLatch | TxAvailable | RxEarly | IntReq);
+ ETH_CMD(dev, intr_enable);
/* Tell the adapter where the RX ring is located */
issue_and_wait(dev,UpStall); /* Stall and set the UplistPtr */
ETH_OUTL(dev, (u32)&rx_ring[rx_next], UpListPtr);
- ETH_CMD(dev, RxEnable); /* Enable the receiver. */
+ ETH_CMD(dev, RxEnable); /* Enable the receiver. */
issue_and_wait(dev,UpUnstall);
/* Send the Individual Address Setup frame */
/* Tell the adapter where the TX ring is located */
- ETH_CMD(dev, TxEnable); /* Enable transmitter. */
+ ETH_CMD(dev, TxEnable); /* Enable transmitter. */
issue_and_wait(dev, DownStall); /* Stall and set the DownListPtr. */
ETH_OUTL(dev, (u32)&tx_ring[tx_cur], DownListPtr);
issue_and_wait(dev, DownUnstall);
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
+ ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
+ issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
}
status = 1;
-
+
Done:
return status;
}
}
if (ETH_STATUS(dev) & DownComplete) /* If DownLoad Complete ACK the bit */
{
- ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
- issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
+ ETH_CMD(dev, AckIntr | DownComplete); /* acknowledge the indication bit */
+ issue_and_wait(dev, DownStall); /* stall and clear DownListPtr */
ETH_OUTL(dev, 0, DownListPtr);
issue_and_wait(dev, DownUnstall);
}
status = le32_to_cpu(rx_ring[rx_next].status); /* packet status */
while (status & (1<<15))
- {
+ {
/* A packet has been received */
- if (status & (1<<15))
+ if (status & (1<<15))
{
/* A valid frame received */
-
+
length = le32_to_cpu(rx_ring[rx_next].status) & 0x1fff; /* length is in bits 0 - 12 */
-
+
/* Pass the packet up to the protocol layers */
NetReceive((uchar *)le32_to_cpu(rx_ring[rx_next].addr), length);
void eth_3com_halt(struct eth_device* dev)
{
- if (!(dev->iobase))
+ if (!(dev->iobase))
{
goto Done;
}
issue_and_wait(dev, RxDisable);
issue_and_wait(dev, TxDisable);
-// free(tx_ring); /* release memory allocated to the DPD and UPD rings */
-// free(rx_ring);
+/* free(tx_ring); /###* release memory allocated to the DPD and UPD rings */
+/* free(rx_ring); */
Done:
return;
}
-static void init_rx_ring(struct eth_device* dev)
+static void init_rx_ring(struct eth_device* dev)
{
int i;
rx_next = 0;
}
-static void purge_tx_ring(struct eth_device* dev)
+static void purge_tx_ring(struct eth_device* dev)
{
int i;
}
}
-static void read_hw_addr(struct eth_device* dev, bd_t *bis)
+static void read_hw_addr(struct eth_device* dev, bd_t *bis)
{
u8 hw_addr[ETH_ALEN];
unsigned int eeprom[0x40];
unsigned int checksum = 0;
int i, j, timer;
- /* Read the station address from the EEPROM. */
+ /* Read the station address from the EEPROM. */
- EL3WINDOW(dev, 0);
+ EL3WINDOW(dev, 0);
for (i = 0; i < 0x40; i++)
{
- ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
- /* Pause for at least 162 us. for the read to take place. */
- for (timer = 10; timer >= 0; timer--)
+ ETH_OUTW(dev, EEPROM_Read + i, Wn0EepromCmd);
+ /* Pause for at least 162 us. for the read to take place. */
+ for (timer = 10; timer >= 0; timer--)
{
- udelay(162);
- if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
- break;
- }
- eeprom[i] = ETH_INW(dev, Wn0EepromData);
- }
+ udelay(162);
+ if ((ETH_INW(dev, Wn0EepromCmd) & 0x8000) == 0)
+ break;
+ }
+ eeprom[i] = ETH_INW(dev, Wn0EepromData);
+ }
/* Checksum calculation. I'm not sure about this part and there seems to be a bug on the 3com side of things */
- for (i = 0; i < 0x21; i++)
- checksum ^= eeprom[i];
- checksum = (checksum ^ (checksum >> 8)) & 0xff;
+ for (i = 0; i < 0x21; i++)
+ checksum ^= eeprom[i];
+ checksum = (checksum ^ (checksum >> 8)) & 0xff;
- if (checksum != 0xbb)
- printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
+ if (checksum != 0xbb)
+ printf(" *** INVALID EEPROM CHECKSUM %4.4x *** \n", checksum);
- for (i = 0, j = 0; i < 3; i++)
+ for (i = 0, j = 0; i < 3; i++)
{
hw_addr[j++] = (u8)((eeprom[i+10] >> 8) & 0xff);
hw_addr[j++] = (u8)(eeprom[i+10] & 0xff);
/* MAC Address is in window 2, write value from EEPROM to window 2 */
- EL3WINDOW(dev, 2);
- for (i = 0; i < 6; i++)
- ETH_OUTB(dev, hw_addr[i], i);
+ EL3WINDOW(dev, 2);
+ for (i = 0; i < 6; i++)
+ ETH_OUTB(dev, hw_addr[i], i);
for (j = 0; j < ETH_ALEN; j+=2)
{
hw_addr[j+1] = (u8)((ETH_INW(dev, j) >> 8) & 0xff);
}
- for (i=0;i<ETH_ALEN;i++)
+ for (i=0;i<ETH_ALEN;i++)
{
- if (hw_addr[i] != bis->bi_enetaddr[i])
+ if (hw_addr[i] != bis->bi_enetaddr[i])
{
/* printf("Warning: HW address don't match:\n"); */
/* printf("Address in 3Com Window 2 is " */
bis->bi_enetaddr[4] == 0 && bis->bi_enetaddr[5] == 0)
{
- sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
- hw_addr[0], hw_addr[1], hw_addr[2],
- hw_addr[3], hw_addr[4], hw_addr[5]);
+ sprintf(buffer, "%02X:%02X:%02X:%02X:%02X:%02X",
+ hw_addr[0], hw_addr[1], hw_addr[2],
+ hw_addr[3], hw_addr[4], hw_addr[5]);
setenv("ethaddr", buffer);
}
}
Done:
return;
}
-
projects / people / ms / u-boot.git / blobdiff