arm: socfpga: Remove CV-specific parts from AV-SoCDK

[people/ms/u-boot.git] / board / altera / arria5-socdk / qts / sdram_config.h

diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h
index f6d51ca8efbf27753aeba6e3249f22e5c75fcda5..2e26ae5bd855a318d7bbf4c86e9e05c70241355b 100644 (file)
--- a/board/altera/arria5-socdk/qts/sdram_config.h
+++ b/board/altera/arria5-socdk/qts/sdram_config.h
@@ -20,7 +20,6 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL                        6
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL                  0
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL                 7
-#ifdef CONFIG_SOCFPGA_ARRIA5
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        19
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        139
@@ -32,19 +31,6 @@
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        19
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 26
-#else
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC                        104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI            3120
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD             6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR              6
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR             4
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP                        3
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS                        14
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC                 20
-#endif /* CONFIG_SOCFPGA_ARRIA5 */
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD                        4
 #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT                512