drivers, block: remove sil680 driver

[people/ms/u-boot.git] / board / amcc / acadia / memory.c

diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 5375d36c9b580d1d5b757692a8b1a67aa02dbf52..36500da6f4f7ed1c814c13ee4335c3234dac2829 100644 (file)
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* define DEBUG for debugging output (obviously ;-)) */
@@ -29,22 +13,18 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <asm/gpio.h>
+#include <asm/ppc4xx-gpio.h>
 
-/*
- * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
- */
-void sdram_init(void)
-{
-       return;
-}
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void board_pll_init_f(void);
 
 static void cram_bcr_write(u32 wr_val)
 {
        wr_val <<= 2;
 
        /* set CRAM_CRE to 1 */
-       gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
+       gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
 
        /* Write BCR to CRAM on CS1 */
        out32(wr_val + 0x00200000, 0);
@@ -58,46 +38,48 @@ static void cram_bcr_write(u32 wr_val)
        eieio();
 
        /* set CRAM_CRE back to 0 (normal operation) */
-       gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
+       gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
 
        return;
 }
 
-long int initdram(int board_type)
+int dram_init(void)
 {
+       int i;
        u32 val;
 
        /* 1. EBC need to program READY, CLK, ADV for ASync mode */
-       gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-       gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-       gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-       gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
 
        /* 2. EBC in Async mode */
-       mtebc(pb1ap, 0x078F1EC0);
-       mtebc(pb2ap, 0x078F1EC0);
-       mtebc(pb1cr, 0x000BC000);
-       mtebc(pb2cr, 0x020BC000);
+       mtebc(PB1AP, 0x078F1EC0);
+       mtebc(PB2AP, 0x078F1EC0);
+       mtebc(PB1CR, 0x000BC000);
+       mtebc(PB2CR, 0x020BC000);
 
        /* 3. Set CRAM in Sync mode */
        cram_bcr_write(0x7012);         /* CRAM burst setting */
 
        /* 4. EBC in Sync mode */
-       mtebc(pb1ap, 0x9C0201C0);
-       mtebc(pb2ap, 0x9C0201C0);
+       mtebc(PB1AP, 0x9C0201C0);
+       mtebc(PB2AP, 0x9C0201C0);
 
        /* Set GPIO pins back to alternate function */
-       gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-       gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+       gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
 
        /* Config EBC to use RDY */
-       mfsdr(sdrultra0, val);
-       mtsdr(sdrultra0, val | 0x04000000);
+       mfsdr(SDR0_ULTRA0, val);
+       mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
 
-       return (CFG_MBYTES_RAM << 20);
-}
+       /* Wait a short while, since for NAND booting this is too fast */
+       for (i=0; i<200000; i++)
+               ;
 
-int testdram(void)
-{
-       return (0);
+       gd->ram_size = CONFIG_SYS_MBYTES_RAM << 20;
+
+       return 0;
 }