drivers, block: remove sil680 driver

[people/ms/u-boot.git] / board / amcc / acadia / pll.c

diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c
index 452961d345c3267703a777521e17406ee3580902..d868582ba90d53bc4384e2d1f9bba2052ecfd133 100644 (file)
--- a/board/amcc/acadia/pll.c
+++ b/board/amcc/acadia/pll.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -53,9 +37,9 @@ void board_pll_init_f(void)
        /* Initialize PLL */
        mtcpr(CPR0_PLLC, 0x0000033c);
        mtcpr(CPR0_PLLD, 0x0c010200);
-       mtcpr(CPC0_PRIMAD, 0x04060c0c);
-       mtcpr(CPC0_PERD0, 0x000c0000);  /* SPI clk div. eq. OPB clk div. */
-       mtcpr(CPR0_CLKUP, 0x40000000);
+       mtcpr(CPR0_PRIMAD, 0x04060c0c);
+       mtcpr(CPR0_PERD0, 0x000c0000);  /* SPI clk div. eq. OPB clk div. */
+       mtcpr(CPR0_CLKUPD, 0x40000000);
 }
 
 #elif defined(PLLMR0_266_160_80)
@@ -85,10 +69,10 @@ void board_pll_init_f(void)
        /* Initialize PLL */
        mtcpr(CPR0_PLLC, 0x20000238);
        mtcpr(CPR0_PLLD, 0x03010400);
-       mtcpr(CPC0_PRIMAD, 0x03050a0a);
-       mtcpr(CPC0_PERC0, 0x00000000);
-       mtcpr(CPC0_PERD0, 0x070a0707);  /* SPI clk div. eq. OPB clk div. */
-       mtcpr(CPC0_PERD1, 0x07323200);
+       mtcpr(CPR0_PRIMAD, 0x03050a0a);
+       mtcpr(CPR0_PERC0, 0x00000000);
+       mtcpr(CPR0_PERD0, 0x070a0707);  /* SPI clk div. eq. OPB clk div. */
+       mtcpr(CPR0_PERD1, 0x07323200);
        mtcpr(CPR0_CLKUP, 0x40000000);
 }
 
@@ -119,9 +103,9 @@ void board_pll_init_f(void)
        /* Initialize PLL */
        mtcpr(CPR0_PLLC, 0x0000033C);
        mtcpr(CPR0_PLLD, 0x0a010000);
-       mtcpr(CPC0_PRIMAD, 0x02040808);
-       mtcpr(CPC0_PERD0, 0x02080505);  /* SPI clk div. eq. OPB clk div. */
-       mtcpr(CPC0_PERD1, 0xA6A60300);
+       mtcpr(CPR0_PRIMAD, 0x02040808);
+       mtcpr(CPR0_PERD0, 0x02080505);  /* SPI clk div. eq. OPB clk div. */
+       mtcpr(CPR0_PERD1, 0xA6A60300);
        mtcpr(CPR0_CLKUP, 0x40000000);
 }
 
@@ -145,51 +129,9 @@ void board_pll_init_f(void)
        /* Initialize PLL */
        mtcpr(CPR0_PLLC, 0x000003BC);
        mtcpr(CPR0_PLLD, 0x06060600);
-       mtcpr(CPC0_PRIMAD, 0x02020004);
-       mtcpr(CPC0_PERD0, 0x04002828);  /* SPI clk div. eq. OPB clk div. */
-       mtcpr(CPC0_PERD1, 0xC8C81600);
+       mtcpr(CPR0_PRIMAD, 0x02020004);
+       mtcpr(CPR0_PERD0, 0x04002828);  /* SPI clk div. eq. OPB clk div. */
+       mtcpr(CPR0_PERD1, 0xC8C81600);
        mtcpr(CPR0_CLKUP, 0x40000000);
 }
 #endif                         /* CPU_<speed>_405EZ */
-
-#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
-/*
- * Get timebase clock frequency
- */
-unsigned long get_tbclk(void)
-{
-       unsigned long cpr_plld;
-       unsigned long cpr_primad;
-       unsigned long primad_cpudv;
-       unsigned long pllFbkDiv;
-       unsigned long freqProcessor;
-
-       /*
-        * Read PLL Mode registers
-        */
-       mfcpr(CPR0_PLLD, cpr_plld);
-
-       /*
-        * Read CPR_PRIMAD register
-        */
-       mfcpr(CPC0_PRIMAD, cpr_primad);
-
-       /*
-        * Determine CPU clock frequency
-        */
-       primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
-       if (primad_cpudv == 0)
-               primad_cpudv = 16;
-
-       /*
-        * Determine FBK_DIV.
-        */
-       pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
-       if (pllFbkDiv == 0)
-               pllFbkDiv = 256;
-
-       freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
-
-       return (freqProcessor);
-}
-#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */