drivers, block: remove sil680 driver

[people/ms/u-boot.git] / board / amcc / bamboo / bamboo.c

diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 6f5d0a60a3112ff7777af8d235ddb3185d632828..9f642071cc5d93759752ae73bb7d9369bc13b9f8 100644 (file)
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2005-2007
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -28,11 +12,12 @@
 #include <asm/ppc440.h>
 #include "bamboo.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 void ext_bus_cntlr_init(void);
 void configure_ppc440ep_pins(void);
 int is_nand_selected(void);
 
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 /*************************************************************************
  *
  * Bamboo has one bank onboard sdram (plus DIMM)
@@ -194,7 +179,6 @@ const unsigned char cfg_simulate_spd_eeprom[128] = {
        0,
        0
 };
-#endif
 
 #if 0
 {         /* GPIO   Alternate1       Alternate2        Alternate3 */
@@ -454,17 +438,11 @@ int checkboard(void)
 }
 
 
-phys_size_t initdram (int board_type)
+int dram_init(void)
 {
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
-       long dram_size;
+       gd->ram_size = spd_sdram();
 
-       dram_size = spd_sdram();
-
-       return dram_size;
-#else
-       return CONFIG_SYS_MBYTES_SDRAM << 20;
-#endif
+       return 0;
 }
 
 /*----------------------------------------------------------------------------+
@@ -1810,23 +1788,12 @@ void configure_ppc440ep_pins(void)
        if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
        {
                update_ndfc_ios(gpio_tab);
-
-#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
                mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
                      SDR0_CUST0_NDFC_ENABLE    |
                      SDR0_CUST0_NDFC_BW_8_BIT  |
                      SDR0_CUST0_NDFC_ARE_MASK  |
                      SDR0_CUST0_CHIPSELGAT_EN1 |
                      SDR0_CUST0_CHIPSELGAT_EN2);
-#else
-               mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL   |
-                     SDR0_CUST0_NDFC_ENABLE    |
-                     SDR0_CUST0_NDFC_BW_8_BIT  |
-                     SDR0_CUST0_NDFC_ARE_MASK  |
-                     SDR0_CUST0_CHIPSELGAT_EN0 |
-                     SDR0_CUST0_CHIPSELGAT_EN2);
-#endif
-
                ndfc_selection_in_fpga();
        }
        else
@@ -1913,7 +1880,7 @@ void configure_ppc440ep_pins(void)
        if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
        {
                mfsdr(SDR0_MFR, sdr0_mfr);
-               sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
+               sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;
                mtsdr(SDR0_MFR, sdr0_mfr);
        }