rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / board / amcc / yosemite / yosemite.c

diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 05be40acdf99dfd5fb60362fccbc862719c7b2a1..3982896cb3282abad57b95beed10c01b5aee33ef 100644 (file)
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -31,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 int board_early_init_f(void)
 {
@@ -107,18 +107,18 @@ int board_early_init_f(void)
        mtsdr(sdr_pfc1, 0x00048000);    /* Pin function: UART0 has 4 pins */
 
        /*clear tmrclk divisor */
-       *(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+       *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
 
        /*enable ethernet */
-       *(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+       *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
 
 #ifdef CONFIG_440EP
        /*enable usb 1.1 fs device and remove usb 2.0 reset */
-       *(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+       *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
 #endif
 
        /*get rid of flash write protect */
-       *(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+       *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
 
        return 0;
 }
@@ -167,7 +167,7 @@ int misc_init_r (void)
 
        /* Monitor protection ON by default */
        (void)flash_protect(FLAG_PROTECT_SET,
-                           -CFG_MONITOR_LEN,
+                           -CONFIG_SYS_MONITOR_LEN,
                            0xffffffff,
                            &flash_info[0]);
 
@@ -186,8 +186,8 @@ int checkboard(void)
        printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 #endif
 
-       rev = in_8((void *)(CFG_BCSR_BASE + 0));
-       val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
+       rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+       val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
        printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
        if (s != NULL) {
@@ -329,7 +329,7 @@ phys_size_t initdram(int board)
        sdram_tr1_set(0x08000000, &tr1_bank2);
        mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-       return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);     /* return bytes */
+       return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);       /* return bytes */
 }
 
 /*************************************************************************
@@ -395,7 +395,7 @@ int pci_pre_init(struct pci_controller *hose)
  *     may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
        /*--------------------------------------------------------------------------+
@@ -409,14 +409,14 @@ void pci_target_init(struct pci_controller *hose)
          | Make this region non-prefetchable.
          +--------------------------------------------------------------------------*/
        out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
-       out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);   /* PMM0 Local Address */
+       out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);        /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 
        out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
-       out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-       out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
+       out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);  /* PMM0 Local Address */
+       out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);       /* PMM0 PCI Low Address */
        out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
        out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 
@@ -431,8 +431,8 @@ void pci_target_init(struct pci_controller *hose)
 
        /* Program the board's subsystem id/vendor id */
        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-                             CFG_PCI_SUBSYS_VENDORID);
-       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+                             CONFIG_SYS_PCI_SUBSYS_VENDORID);
+       pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
        /* Configure command register as bus master */
        pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -446,13 +446,13 @@ void pci_target_init(struct pci_controller *hose)
        pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
        unsigned short temp_short;
@@ -467,7 +467,7 @@ void pci_master_init(struct pci_controller *hose)
                              temp_short | PCI_COMMAND_MASTER |
                              PCI_COMMAND_MEMORY);
 }
-#endif                         /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif                         /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -508,5 +508,5 @@ void hw_watchdog_reset(void)
 void board_reset(void)
 {
        /* give reset to BCSR */
-       *(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
+       *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
 }