mx6: ddr: Allow changing REFSEL and REFR fields

[people/ms/u-boot.git] / board / barco / platinum / spl_titanium.c

diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c
index a3a42551b0540c23a6ede0d3e21fd25518683b46..d1ba85ab82c8dd50e1f1c27f5fe699c2ec551f1c 100644 (file)
--- a/board/barco/platinum/spl_titanium.c
+++ b/board/barco/platinum/spl_titanium.c
@@ -141,6 +141,8 @@ static void spl_dram_init(int width)
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
                .ddr_type = DDR_TYPE_DDR3,
+               .refsel = 1,            /* Refresh cycles at 32KHz */
+               .refr = 7,              /* 8 refresh commands per refresh cycle */
        };
 
        mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);