cgtqmx6eval: Add SPI NOR flash support

[people/ms/u-boot.git] / board / congatec / cgtqmx6eval / cgtqmx6eval.c

diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index cf5607b2c808c3ac09491c86a498e3cca1aa1c4f..04582294440ccd2d3d1dd792c695b39c98a13e5b 100644 (file)
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -45,6 +45,10 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
+       PAD_CTL_SPEED_MED |             \
+       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 #define MX6Q_QMX6_PFUZE_MUX            IMX_GPIO_NR(6, 9)
 
 
@@ -152,6 +156,13 @@ static iomux_v3_cfg_t enet_pads_ar8035[] = {
        MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+       MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 struct i2c_pads_info i2c_pad_info1 = {
        .scl = {
@@ -381,6 +392,14 @@ static void setup_iomux_uart(void)
        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 
+#ifdef CONFIG_MXC_SPI
+static void setup_spi(void)
+{
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+       gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+}
+#endif
+
 #ifdef CONFIG_FSL_ESDHC
 static struct fsl_esdhc_cfg usdhc_cfg[] = {
        {USDHC2_BASE_ADDR},
@@ -647,6 +666,9 @@ int board_early_init_f(void)
        setup_iomux_uart();
        setup_display();
 
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
        return 0;
 }
 
@@ -671,6 +693,13 @@ int checkboard(void)
        return 0;
 }
 
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+       return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
+}
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
        /* 4 bit bus width */