imx6: geam6ul: Add NAND support

[people/ms/u-boot.git] / board / engicam / geam6ul / geam6ul.c

diff --git a/board/engicam/geam6ul/geam6ul.c b/board/engicam/geam6ul/geam6ul.c
index 85308456efa2cdb97ee91fa100923a02b384b284..40f20a9bec28c2016262770456f6f6cc59a3604b 100644 (file)
--- a/board/engicam/geam6ul/geam6ul.c
+++ b/board/engicam/geam6ul/geam6ul.c
@@ -13,6 +13,7 @@
 #include <linux/sizes.h>
 
 #include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/sys_proto.h>
@@ -36,11 +37,81 @@ int board_early_init_f(void)
        return 0;
 }
 
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0         (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1         (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+                               PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2         (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+static iomux_v3_cfg_t const nand_pads[] = {
+       MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+       MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
+};
+
+static void setup_gpmi_nand(void)
+{
+       struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+       /* config gpmi nand iomux */
+       imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
+
+       clrbits_le32(&mxc_ccm->CCGR4,
+                    MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+       /*
+        * config gpmi and bch clock to 100 MHz
+        * bch/gpmi select PLL2 PFD2 400M
+        * 100M = 400M / 4
+        */
+       clrbits_le32(&mxc_ccm->cscmr1,
+                    MXC_CCM_CSCMR1_BCH_CLK_SEL |
+                    MXC_CCM_CSCMR1_GPMI_CLK_SEL);
+       clrsetbits_le32(&mxc_ccm->cscdr1,
+                       MXC_CCM_CSCDR1_BCH_PODF_MASK |
+                       MXC_CCM_CSCDR1_GPMI_PODF_MASK,
+                       (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
+                       (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
+
+       /* enable gpmi and bch clock gating */
+       setbits_le32(&mxc_ccm->CCGR4,
+                    MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+                    MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+                    MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+
+       /* enable apbh clock gating */
+       setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif /* CONFIG_NAND_MXS */
+
 int board_init(void)
 {
        /* Address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_NAND_MXS
+       setup_gpmi_nand();
+#endif
+
        return 0;
 }