*/
#include <common.h>
+#include <mmc.h>
#include <asm/io.h>
#include <asm/gpio.h>
return 0;
}
+#ifdef CONFIG_ENV_IS_IN_MMC
+int board_mmc_get_env_dev(int devno)
+{
+ /* dev 0 for SD/eSD, dev 1 for MMC/eMMC */
+ return (devno == 3) ? 1 : 0;
+}
+
+static void mmc_late_init(void)
+{
+ char cmd[32];
+ char mmcblk[32];
+ u32 dev_no = mmc_get_env_dev();
+
+ setenv_ulong("mmcdev", dev_no);
+
+ /* Set mmcblk env */
+ sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no);
+ setenv("mmcroot", mmcblk);
+
+ sprintf(cmd, "mmc dev %d", dev_no);
+ run_command(cmd, 0);
+}
+#endif
+
+int board_late_init(void)
+{
+ switch ((imx6_src_get_boot_mode() & IMX6_BMODE_MASK) >>
+ IMX6_BMODE_SHIFT) {
+ case IMX6_BMODE_SD:
+ case IMX6_BMODE_ESD:
+ case IMX6_BMODE_MMC:
+ case IMX6_BMODE_EMMC:
+#ifdef CONFIG_ENV_IS_IN_MMC
+ mmc_late_init();
+#endif
+ setenv("modeboot", "mmcboot");
+ break;
+ default:
+ setenv("modeboot", "");
+ break;
+ }
+
+ if (is_mx6dq())
+ setenv("fdt_file", "imx6q-icore-rqs.dtb");
+ else if(is_mx6dl() || is_mx6solo())
+ setenv("fdt_file", "imx6dl-icore-rqs.dtb");
+
+ return 0;
+}
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
-struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC3_BASE_ADDR, 1, 4},
+ {USDHC4_BASE_ADDR, 1, 8},
};
int board_mmc_getcd(struct mmc *mmc)
switch (cfg->esdhc_base) {
case USDHC3_BASE_ADDR:
+ case USDHC4_BASE_ADDR:
ret = 1;
break;
}
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
- * mmc0 USDHC3
+ * mmc0 USDHC3
+ * mmc1 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
+ case 1:
+ SETUP_IOMUX_PADS(usdhc4_pads);
+ usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+ break;
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);