* (C) Copyright 2001-2003
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <console.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void __ft_board_setup(void *blob, bd_t *bd);
#undef FPGA_DEBUG
const unsigned char fpgadata[] =
{
#if defined(CONFIG_CPCI405_VER2)
-# if defined(CONFIG_CPCI405AB)
-# include "fpgadata_cpci405ab.c"
-# else
-# include "fpgadata_cpci4052.c"
-# endif
-#else
-# include "fpgadata_cpci405.c"
+# include "fpgadata_cpci4052.c"
#endif
};
* include common fpga code (for esd boards)
*/
#include "../common/fpga.c"
-#include "../common/auto_update.h"
-
-#if defined(CONFIG_CPCI405AB)
-au_image_t au_image[] = {
- {"cpci405ab/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci405ab/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci405ab/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
- {"cpci405ab/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"cpci405ab/postinst.img", 0, 0, AU_SCRIPT},
-};
-#else
-#if defined(CONFIG_CPCI405_VER2)
-au_image_t au_image[] = {
- {"cpci4052/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci4052/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci4052/pImage.initrd", 0xffcc0000, 0x00300000, AU_NOR},
- {"cpci4052/u-boot.img", 0xfffc0000, 0x00040000, AU_FIRMWARE},
- {"cpci4052/postinst.img", 0, 0, AU_SCRIPT},
-};
-#else
-au_image_t au_image[] = {
- {"cpci405/preinst.img", 0, -1, AU_SCRIPT},
- {"cpci405/pImage", 0xffc00000, 0x000c0000, AU_NOR},
- {"cpci405/pImage.initrd", 0xffcc0000, 0x00310000, AU_NOR},
- {"cpci405/u-boot.img", 0xfffd0000, 0x00030000, AU_FIRMWARE},
- {"cpci405/postinst.img", 0, 0, AU_SCRIPT},
-};
-#endif
-#endif
-
-int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
/* Prototypes */
int cpci405_version(void);
-int gunzip(void *, int, unsigned char *, unsigned long *);
void lxt971_no_sleep(void);
int board_early_init_f(void)
* First pull fpga-prg pin low,
* to disable fpga logic (on version 2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
- out32(GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out_be32((void *)GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG); /* setup for output */
+ out_be32((void *)GPIO0_OR, CONFIG_SYS_FPGA_PRG); /* set output pins to high */
+ out_be32((void *)GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
#if defined(CONFIG_CPCI405_6U)
if (cpci405_version() == 3) {
- mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF99); /* set int polarities */
} else {
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
}
#else
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
#endif
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,
* INT0 highest priority */
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
return 0;
}
int cpci405_host(void)
{
- if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
+ if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
return -1; /* yes, board is cpci405 host */
else
return 0; /* no, board is cpci405 adapter */
int cpci405_version(void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
unsigned long value;
/*
* Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
/*
* Restore GPIO settings
*/
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
switch (value) {
case 0x00180000:
int misc_init_r (void)
{
- unsigned long cntrl0Reg;
+ unsigned long CPC0_CR0Reg;
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE,
}
/* restore gpio/cs settings */
- mtdcr(cntrl0, cntrl0Reg);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg);
puts("FPGA: ");
/*
* Select cts (and not dsr) on uart1
*/
- cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00001000);
+ CPC0_CR0Reg = mfdcr(CPC0_CR0);
+ mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000);
return 0;
}
int len;
#endif
char str[64];
- int i = getenv_r("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
unsigned short ver;
puts("Board: ");
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
{
int rc;
fdt_strerror(rc));
}
}
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_CPCI405AB)
-#define ONE_WIRE_CLEAR out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE), \
- in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE)) | \
- CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-
-#define ONE_WIRE_SET out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE), \
- in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_MODE)) & \
- ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
-
-#define ONE_WIRE_GET (in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR + \
- CONFIG_SYS_FPGA_STATUS)) & \
- CONFIG_SYS_FPGA_MODE_1WIRE)
-
-/*
- * Generate a 1-wire reset, return 1 if no presence detect was found,
- * return 0 otherwise.
- * (NOTE: Does not handle alarm presence from DS2404/DS1994)
- */
-int OWTouchReset(void)
-{
- int result;
-
- ONE_WIRE_CLEAR;
- udelay(480);
- ONE_WIRE_SET;
- udelay(70);
-
- result = ONE_WIRE_GET;
-
- udelay(410);
- return result;
-}
-
-/*
- * Send 1 a 1-wire write bit.
- * Provide 10us recovery time.
- */
-void OWWriteBit(int bit)
-{
- if (bit) {
- /*
- * write '1' bit
- */
- ONE_WIRE_CLEAR;
- udelay(6);
- ONE_WIRE_SET;
- udelay(64);
- } else {
- /*
- * write '0' bit
- */
- ONE_WIRE_CLEAR;
- udelay(60);
- ONE_WIRE_SET;
- udelay(10);
- }
-}
-
-/*
- * Read a bit from the 1-wire bus and return it.
- * Provide 10us recovery time.
- */
-int OWReadBit(void)
-{
- int result;
-
- ONE_WIRE_CLEAR;
- udelay(6);
- ONE_WIRE_SET;
- udelay(9);
-
- result = ONE_WIRE_GET;
-
- udelay(55);
- return result;
-}
-
-void OWWriteByte(int data)
-{
- int loop;
-
- for (loop = 0; loop < 8; loop++) {
- OWWriteBit(data & 0x01);
- data >>= 1;
- }
-}
-
-int OWReadByte(void)
-{
- int loop, result = 0;
-
- for (loop = 0; loop < 8; loop++) {
- result >>= 1;
- if (OWReadBit())
- result |= 0x80;
- }
-
- return result;
-}
-
-int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- unsigned short val;
- int result;
- int i;
- unsigned char ow_id[6];
- char str[32];
- unsigned char ow_crc;
-
- /*
- * Clear 1-wire bit (open drain with pull-up)
- */
- val = in_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
- CONFIG_SYS_FPGA_MODE));
- val &= ~CONFIG_SYS_FPGA_MODE_1WIRE; /* clear 1-wire bit */
- out_be16((void*)(CONFIG_SYS_FPGA_BASE_ADDR +
- CONFIG_SYS_FPGA_MODE), val);
-
- result = OWTouchReset();
- if (result != 0)
- puts("No 1-wire device detected!\n");
-
- OWWriteByte(0x33); /* send read rom command */
- OWReadByte(); /* skip family code ( == 0x01) */
- for (i = 0; i < 6; i++)
- ow_id[i] = OWReadByte();
- ow_crc = OWReadByte(); /* read crc */
-
- sprintf(str, "%08X%04X",
- *(unsigned int *)&ow_id[0],
- *(unsigned short *)&ow_id[4]);
- printf("Setting environment variable 'ow_id' to %s\n", str);
- setenv("ow_id", str);
-
- return 0;
-}
-U_BOOT_CMD(
- onewire, 1, 1, do_onewire,
- "onewire - Read 1-write ID\n",
- NULL
- );
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT24WC32 */
-#define CONFIG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars */
-
-/*
- * Write backplane ip-address...
- */
-int do_get_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- bd_t *bd = gd->bd;
- char *buf;
- ulong crc;
- char str[32];
- char *ptr;
- IPaddr_t ipaddr;
-
- buf = malloc(CONFIG_ENV_SIZE_2);
- if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0,
- (uchar *)buf, CONFIG_ENV_SIZE_2))
- puts("\nError reading backplane EEPROM!\n");
- else {
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
- if (crc != *(ulong *)buf) {
- printf("ERROR: crc mismatch %08lx %08lx\n",
- crc, *(ulong *)buf);
- return -1;
- }
-
- /*
- * Find bp_ip
- */
- ptr = strstr(buf+4, "bp_ip=");
- if (ptr == NULL) {
- printf("ERROR: bp_ip not found!\n");
- return -1;
- }
- ptr += 6;
- ipaddr = string_to_ip(ptr);
-
- /*
- * Update whole ip-addr
- */
- bd->bi_ip_addr = ipaddr;
- sprintf(str, "%ld.%ld.%ld.%ld",
- (bd->bi_ip_addr & 0xff000000) >> 24,
- (bd->bi_ip_addr & 0x00ff0000) >> 16,
- (bd->bi_ip_addr & 0x0000ff00) >> 8,
- (bd->bi_ip_addr & 0x000000ff));
- setenv("ipaddr", str);
- printf("Updated ip_addr from bp_eeprom to %s!\n", str);
- }
-
- free(buf);
return 0;
}
-U_BOOT_CMD(
- getbpip, 1, 1, do_get_bpip,
- "getbpip - Update IP-Address with Backplane IP-Address\n",
- NULL
- );
-
-/*
- * Set and print backplane ip...
- */
-int do_set_bpip(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- char *buf;
- char str[32];
- ulong crc;
-
- if (argc < 2) {
- puts("ERROR!\n");
- return -1;
- }
-
- printf("Setting bp_ip to %s\n", argv[1]);
- buf = malloc(CONFIG_ENV_SIZE_2);
- memset(buf, 0, CONFIG_ENV_SIZE_2);
- sprintf(str, "bp_ip=%s", argv[1]);
- strcpy(buf+4, str);
- crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2 - 4);
- *(ulong *)buf = crc;
-
- if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2,
- 0, (uchar *)buf, CONFIG_ENV_SIZE_2))
- puts("\nError writing backplane EEPROM!\n");
-
- free(buf);
-
- return 0;
-}
-U_BOOT_CMD(
- setbpip, 2, 1, do_set_bpip,
- "setbpip - Write Backplane IP-Address\n",
- NULL
- );
-
-#endif /* CONFIG_CPCI405AB */
+#endif /* CONFIG_OF_BOARD_SETUP */
projects / people / ms / u-boot.git / blobdiff