]> git.ipfire.org Git - people/ms/u-boot.git/blobdiff - board/freescale/ls1043ardb/ls1043ardb.c
Kconfig: Move CONFIG_FIT and related options to Kconfig
[people/ms/u-boot.git] / board / freescale / ls1043ardb / ls1043ardb.c
index 9032ed36c852274fbf804ea7c361daa4cfefd9ae..ec5fdbfe27ec46ce8ac1b84a17db0b6a9a1d09c9 100644 (file)
@@ -10,6 +10,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
+#include <fdt_support.h>
 #include <hwconfig.h>
 #include <ahci.h>
 #include <mmc.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
 #include <fsl_ifc.h>
+#include <environment.h>
+#include <fsl_sec.h>
 #include "cpld.h"
+#ifdef CONFIG_U_QE
+#include <fsl_qe.h>
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -70,6 +77,7 @@ int dram_init(void)
 int board_early_init_f(void)
 {
        fsl_lsch2_early_init_f();
+
        return 0;
 }
 
@@ -95,11 +103,36 @@ int board_init(void)
        enable_layerscape_ns_access();
 #endif
 
+#ifdef CONFIG_U_QE
+       u_qe_init();
+#endif
+
        return 0;
 }
 
 int config_board_mux(void)
 {
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       u32 usb_pwrfault;
+
+       if (hwconfig("qe-hdlc")) {
+               out_be32(&scfg->rcwpmuxcr0,
+                        (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
+               printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
+                      in_be32(&scfg->rcwpmuxcr0));
+       } else {
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+               out_be32(&scfg->rcwpmuxcr0, 0x3333);
+               out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
+               usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
+                               SCFG_USBPWRFAULT_USB3_SHIFT) |
+                               (SCFG_USBPWRFAULT_DEDICATED <<
+                               SCFG_USBPWRFAULT_USB2_SHIFT) |
+                               (SCFG_USBPWRFAULT_SHARED <<
+                                SCFG_USBPWRFAULT_USB1_SHIFT);
+               out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
+#endif
+       }
        return 0;
 }
 
@@ -107,18 +140,69 @@ int config_board_mux(void)
 int misc_init_r(void)
 {
        config_board_mux();
-
+#ifdef CONFIG_SECURE_BOOT
+       /* In case of Secure Boot, the IBR configures the SMMU
+        * to allow only Secure transactions.
+        * SMMU must be reset in bypass mode.
+        * Set the ClientPD bit and Clear the USFCFG Bit
+        */
+       u32 val;
+       val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_SCR0, val);
+       val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
+       out_le32(SMMU_NSCR0, val);
+#endif
+#ifdef CONFIG_FSL_CAAM
+       return sec_init();
+#endif
        return 0;
 }
 #endif
 
+void fdt_del_qe(void *blob)
+{
+       int nodeoff = 0;
+
+       while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
+                               "fsl,qe")) >= 0) {
+               fdt_del_node(blob, nodeoff);
+       }
+}
+
 int ft_board_setup(void *blob, bd_t *bd)
 {
+       u64 base[CONFIG_NR_DRAM_BANKS];
+       u64 size[CONFIG_NR_DRAM_BANKS];
+
+       /* fixup DT for the two DDR banks */
+       base[0] = gd->bd->bi_dram[0].start;
+       size[0] = gd->bd->bi_dram[0].size;
+       base[1] = gd->bd->bi_dram[1].start;
+       size[1] = gd->bd->bi_dram[1].size;
+
+       fdt_fixup_memory_banks(blob, base, size, 2);
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
        fdt_fixup_fman_ethernet(blob);
 #endif
+
+       /*
+        * qe-hdlc and usb multi-use the pins,
+        * when set hwconfig to qe-hdlc, delete usb node.
+        */
+       if (hwconfig("qe-hdlc"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+               fdt_del_node_and_alias(blob, "usb1");
+#endif
+       /*
+        * qe just support qe-uart and qe-hdlc,
+        * if qe-uart and qe-hdlc are not set in hwconfig,
+        * delete qe node.
+        */
+       if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
+               fdt_del_qe(blob);
+
        return 0;
 }