mx6qsabreauto: Fix the EIM clock for the mx6qp variant

[people/ms/u-boot.git] / board / freescale / mx6qsabreauto / mx6qsabreauto.c

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index 5fca4d11e0a828471ff822535d6103aff3dad81e..51bbbc4cdf270fc7f84c07608c635a7bc4cd3412 100644 (file)
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -231,6 +231,33 @@ static void eimnor_cs_setup(void)
        set_chipselect_size(CS0_128);
 }
 
+static void eim_clk_setup(void)
+{
+       struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+       int cscmr1, ccgr6;
+
+
+       /* Turn off EIM clock */
+       ccgr6 = readl(&imx_ccm->CCGR6);
+       ccgr6 &= ~(0x3 << 10);
+       writel(ccgr6, &imx_ccm->CCGR6);
+
+       /*
+        * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+        * and aclk_eim_slow_podf = 01 --> divide by 2
+        * so that we can have EIM at the maximum clock of 132MHz
+        */
+       cscmr1 = readl(&imx_ccm->cscmr1);
+       cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+                   MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+       cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+       writel(cscmr1, &imx_ccm->cscmr1);
+
+       /* Turn on EIM clock */
+       ccgr6 |= (0x3 << 10);
+       writel(ccgr6, &imx_ccm->CCGR6);
+}
+
 static void setup_iomux_eimnor(void)
 {
        imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
@@ -519,6 +546,7 @@ int board_early_init_f(void)
 #ifdef CONFIG_NAND_MXS
        setup_gpmi_nand();
 #endif
+       eim_clk_setup();
 
        return 0;
 }