#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/gpio.h>
-#include <asm/imx-common/mxc_i2c.h>
-#include <asm/imx-common/iomux-v3.h>
-#include <asm/imx-common/boot_mode.h>
-#include <asm/imx-common/video.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <power/pmic.h>
#include <power/pfuze100_pmic.h>
#include "../common/pfuze.h"
-#include <asm/arch/mx6-ddr.h>
#include <usb.h>
DECLARE_GLOBAL_DATA_PTR;
#define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
+#define KEY_VOL_UP IMX_GPIO_NR(1, 4)
+
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8031 PHY Reset */
- MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_enet(void)
{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ SETUP_IOMUX_PADS(enet_pads);
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
- udelay(500);
+ mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+ udelay(100);
}
static iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
};
static iomux_v3_cfg_t const usdhc4_pads[] = {
- MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
static iomux_v3_cfg_t const ecspi1_pads[] = {
- MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const rgb_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
-static void enable_rgb(struct display_info_t const *dev)
+static iomux_v3_cfg_t const bl_pads[] = {
+ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+static void enable_backlight(void)
{
- imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads));
+ SETUP_IOMUX_PADS(bl_pads);
gpio_direction_output(DISP0_PWR_EN, 1);
}
-static struct i2c_pads_info i2c_pad_info1 = {
+static void enable_rgb(struct display_info_t const *dev)
+{
+ SETUP_IOMUX_PADS(rgb_pads);
+ enable_backlight();
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ enable_backlight();
+}
+
+static struct i2c_pads_info mx6q_i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
.gp = IMX_GPIO_NR(4, 13)
}
};
static void setup_spi(void)
{
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+ SETUP_IOMUX_PADS(ecspi1_pads);
}
iomux_v3_cfg_t const pcie_pads[] = {
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
- MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
+ IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
};
static void setup_pcie(void)
{
- imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+ SETUP_IOMUX_PADS(pcie_pads);
}
iomux_v3_cfg_t const di0_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
}
#ifdef CONFIG_FSL_ESDHC
#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
+int board_mmc_get_env_dev(int devno)
+{
+ return devno - 1;
+}
+
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
/*
* According to the board_mmc_init() the following map is done:
- * (U-boot device node) (Physical Port)
+ * (U-Boot device node) (Physical Port)
* mmc0 SD2
* mmc1 SD3
* mmc2 eMMC
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ SETUP_IOMUX_PADS(usdhc2_pads);
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
gpio_direction_input(USDHC3_CD_GPIO);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
break;
case 2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
break;
default:
switch (reg & 0x3) {
case 0x1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x2:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x3:
- imx_iomux_v3_setup_multiple_pads(
- usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+ SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
}
#endif
-int mx6_rgmii_rework(struct phy_device *phydev)
+static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
int board_phy_config(struct phy_device *phydev)
{
- mx6_rgmii_rework(phydev);
+ ar8031_phy_fixup(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
imx_enable_hdmi_phy();
}
-static void enable_lvds(struct display_info_t const *dev)
-{
- struct iomuxc *iomux = (struct iomuxc *)
- IOMUXC_BASE_ADDR;
- u32 reg = readl(&iomux->gpr[2]);
- reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
- IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
- writel(reg, &iomux->gpr[2]);
-}
-
struct display_info_t const displays[] = {{
.bus = -1,
.addr = 0,
.refresh = 60,
.xres = 1024,
.yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
.refresh = 60,
.xres = 1024,
.yres = 768,
- .pixclock = 15385,
- .left_margin = 220,
- .right_margin = 40,
- .upper_margin = 21,
- .lower_margin = 7,
- .hsync_len = 60,
- .vsync_len = 10,
+ .pixclock = 15384,
+ .left_margin = 160,
+ .right_margin = 24,
+ .upper_margin = 29,
+ .lower_margin = 3,
+ .hsync_len = 136,
+ .vsync_len = 6,
.sync = FB_SYNC_EXT,
.vmode = FB_VMODE_NONINTERLACED
} }, {
int reg;
/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
- imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
+ SETUP_IOMUX_PADS(di0_pads);
enable_ipu_clock();
imx_setup_hdmi();
#define UCTRL_PWR_POL (1 << 9)
static iomux_v3_cfg_t const usb_otg_pads[] = {
- MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usb_hc1_pads[] = {
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_usb(void)
{
- imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
- ARRAY_SIZE(usb_otg_pads));
+ SETUP_IOMUX_PADS(usb_otg_pads);
/*
* set daisy chain for otg_pin_id on 6q.
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
- imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
- ARRAY_SIZE(usb_hc1_pads));
+ SETUP_IOMUX_PADS(usb_hc1_pads);
}
int board_ehci_hcd_init(int port)
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-
+ if (is_mx6dq() || is_mx6dqp())
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+ else
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
#ifdef CONFIG_USB_EHCI_MX6
setup_usb();
#endif
int power_init_board(void)
{
struct pmic *p;
- unsigned int reg, ret;
+ unsigned int reg;
+ int ret;
p = pfuze_common_init(I2C_PMIC);
if (!p)
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
/* 8 bit bus width */
- {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
{NULL, 0},
};
#endif
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "SABRESD");
+
+ if (is_mx6dqp())
+ env_set("board_rev", "MX6QP");
+ else if (is_mx6dq())
+ env_set("board_rev", "MX6Q");
+ else if (is_mx6sdl())
+ env_set("board_rev", "MX6DL");
+#endif
+
return 0;
}
}
#ifdef CONFIG_SPL_BUILD
+#include <asm/arch/mx6-ddr.h>
#include <spl.h>
#include <libfdt.h>
-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
- .dram_sdclk_0 = 0x00020030,
- .dram_sdclk_1 = 0x00020030,
- .dram_cas = 0x00020030,
- .dram_ras = 0x00020030,
- .dram_reset = 0x00020030,
- .dram_sdcke0 = 0x00003000,
- .dram_sdcke1 = 0x00003000,
- .dram_sdba2 = 0x00000000,
- .dram_sdodt0 = 0x00003030,
- .dram_sdodt1 = 0x00003030,
- .dram_sdqs0 = 0x00000030,
- .dram_sdqs1 = 0x00000030,
- .dram_sdqs2 = 0x00000030,
- .dram_sdqs3 = 0x00000030,
- .dram_sdqs4 = 0x00000030,
- .dram_sdqs5 = 0x00000030,
- .dram_sdqs6 = 0x00000030,
- .dram_sdqs7 = 0x00000030,
- .dram_dqm0 = 0x00020030,
- .dram_dqm1 = 0x00020030,
- .dram_dqm2 = 0x00020030,
- .dram_dqm3 = 0x00020030,
- .dram_dqm4 = 0x00020030,
- .dram_dqm5 = 0x00020030,
- .dram_dqm6 = 0x00020030,
- .dram_dqm7 = 0x00020030,
-};
-
-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
- .grp_ddr_type = 0x000C0000,
- .grp_ddrmode_ctl = 0x00020000,
- .grp_ddrpke = 0x00000000,
- .grp_addds = 0x00000030,
- .grp_ctlds = 0x00000030,
- .grp_ddrmode = 0x00020000,
- .grp_b0ds = 0x00000030,
- .grp_b1ds = 0x00000030,
- .grp_b2ds = 0x00000030,
- .grp_b3ds = 0x00000030,
- .grp_b4ds = 0x00000030,
- .grp_b5ds = 0x00000030,
- .grp_b6ds = 0x00000030,
- .grp_b7ds = 0x00000030,
-};
-
-const struct mx6_mmdc_calibration mx6_mmcd_calib = {
- .p0_mpwldectrl0 = 0x001F001F,
- .p0_mpwldectrl1 = 0x001F001F,
- .p1_mpwldectrl0 = 0x00440044,
- .p1_mpwldectrl1 = 0x00440044,
- .p0_mpdgctrl0 = 0x434B0350,
- .p0_mpdgctrl1 = 0x034C0359,
- .p1_mpdgctrl0 = 0x434B0350,
- .p1_mpdgctrl1 = 0x03650348,
- .p0_mprddlctl = 0x4436383B,
- .p1_mprddlctl = 0x39393341,
- .p0_mpwrdlctl = 0x35373933,
- .p1_mpwrdlctl = 0x48254A36,
-};
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ gpio_direction_input(KEY_VOL_UP);
-static struct mx6_ddr3_cfg mem_ddr = {
- .mem_speed = 1600,
- .density = 4,
- .width = 64,
- .banks = 8,
- .rowaddr = 14,
- .coladdr = 10,
- .pagesz = 2,
- .trcd = 1375,
- .trcmin = 4875,
- .trasmin = 3500,
-};
+ /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
+ return gpio_get_value(KEY_VOL_UP);
+}
+#endif
static void ccgr_init(void)
{
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
- /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
- writel(0x007F007F, &iomux->gpr[6]);
- writel(0x007F007F, &iomux->gpr[7]);
+ if (is_mx6dqp()) {
+ /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+ writel(0x77177717, &iomux->gpr[6]);
+ writel(0x77177717, &iomux->gpr[7]);
+ } else {
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+ }
}
-/*
- * This section requires the differentiation between iMX6 Sabre boards, but
- * for now, it will configure only for the mx6q variant.
- */
-static void spl_dram_init(void)
+static int mx6q_dcd_table[] = {
+ 0x020e0798, 0x000C0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x43270338,
+ 0x021b0840, 0x03200314,
+ 0x021b483c, 0x431A032F,
+ 0x021b4840, 0x03200263,
+ 0x021b0848, 0x4B434748,
+ 0x021b4848, 0x4445404C,
+ 0x021b0850, 0x38444542,
+ 0x021b4850, 0x4935493A,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x09444040,
+ 0x021b000c, 0x555A7975,
+ 0x021b0010, 0xFF538F64,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x005A1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0000, 0x831A0000,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+};
+
+static int mx6qp_dcd_table[] = {
+ 0x020e0798, 0x000c0000,
+ 0x020e0758, 0x00000000,
+ 0x020e0588, 0x00000030,
+ 0x020e0594, 0x00000030,
+ 0x020e056c, 0x00000030,
+ 0x020e0578, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e057c, 0x00000030,
+ 0x020e058c, 0x00000000,
+ 0x020e059c, 0x00000030,
+ 0x020e05a0, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e05a8, 0x00000030,
+ 0x020e05b0, 0x00000030,
+ 0x020e0524, 0x00000030,
+ 0x020e051c, 0x00000030,
+ 0x020e0518, 0x00000030,
+ 0x020e050c, 0x00000030,
+ 0x020e05b8, 0x00000030,
+ 0x020e05c0, 0x00000030,
+ 0x020e0774, 0x00020000,
+ 0x020e0784, 0x00000030,
+ 0x020e0788, 0x00000030,
+ 0x020e0794, 0x00000030,
+ 0x020e079c, 0x00000030,
+ 0x020e07a0, 0x00000030,
+ 0x020e07a4, 0x00000030,
+ 0x020e07a8, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e05ac, 0x00000030,
+ 0x020e05b4, 0x00000030,
+ 0x020e0528, 0x00000030,
+ 0x020e0520, 0x00000030,
+ 0x020e0514, 0x00000030,
+ 0x020e0510, 0x00000030,
+ 0x020e05bc, 0x00000030,
+ 0x020e05c4, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001b001e,
+ 0x021b0810, 0x002e0029,
+ 0x021b480c, 0x001b002a,
+ 0x021b4810, 0x0019002c,
+ 0x021b083c, 0x43240334,
+ 0x021b0840, 0x0324031a,
+ 0x021b483c, 0x43340344,
+ 0x021b4840, 0x03280276,
+ 0x021b0848, 0x44383A3E,
+ 0x021b4848, 0x3C3C3846,
+ 0x021b0850, 0x2e303230,
+ 0x021b4850, 0x38283E34,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08c0, 0x24912249,
+ 0x021b48c0, 0x24914289,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x00020036,
+ 0x021b0008, 0x24444040,
+ 0x021b000c, 0x555A7955,
+ 0x021b0010, 0xFF320F64,
+ 0x021b0014, 0x01ff00db,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x005A1023,
+ 0x021b0040, 0x00000027,
+ 0x021b0400, 0x14420000,
+ 0x021b0000, 0x831A0000,
+ 0x021b0890, 0x00400C58,
+ 0x00bb0008, 0x00000000,
+ 0x00bb000c, 0x2891E41A,
+ 0x00bb0038, 0x00000564,
+ 0x00bb0014, 0x00000040,
+ 0x00bb0028, 0x00000020,
+ 0x00bb002c, 0x00000020,
+ 0x021b001c, 0x04088032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x09408030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x00025576,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+};
+
+static int mx6dl_dcd_table[] = {
+ 0x020e0774, 0x000C0000,
+ 0x020e0754, 0x00000000,
+ 0x020e04ac, 0x00000030,
+ 0x020e04b0, 0x00000030,
+ 0x020e0464, 0x00000030,
+ 0x020e0490, 0x00000030,
+ 0x020e074c, 0x00000030,
+ 0x020e0494, 0x00000030,
+ 0x020e04a0, 0x00000000,
+ 0x020e04b4, 0x00000030,
+ 0x020e04b8, 0x00000030,
+ 0x020e076c, 0x00000030,
+ 0x020e0750, 0x00020000,
+ 0x020e04bc, 0x00000030,
+ 0x020e04c0, 0x00000030,
+ 0x020e04c4, 0x00000030,
+ 0x020e04c8, 0x00000030,
+ 0x020e04cc, 0x00000030,
+ 0x020e04d0, 0x00000030,
+ 0x020e04d4, 0x00000030,
+ 0x020e04d8, 0x00000030,
+ 0x020e0760, 0x00020000,
+ 0x020e0764, 0x00000030,
+ 0x020e0770, 0x00000030,
+ 0x020e0778, 0x00000030,
+ 0x020e077c, 0x00000030,
+ 0x020e0780, 0x00000030,
+ 0x020e0784, 0x00000030,
+ 0x020e078c, 0x00000030,
+ 0x020e0748, 0x00000030,
+ 0x020e0470, 0x00000030,
+ 0x020e0474, 0x00000030,
+ 0x020e0478, 0x00000030,
+ 0x020e047c, 0x00000030,
+ 0x020e0480, 0x00000030,
+ 0x020e0484, 0x00000030,
+ 0x020e0488, 0x00000030,
+ 0x020e048c, 0x00000030,
+ 0x021b0800, 0xa1390003,
+ 0x021b080c, 0x001F001F,
+ 0x021b0810, 0x001F001F,
+ 0x021b480c, 0x001F001F,
+ 0x021b4810, 0x001F001F,
+ 0x021b083c, 0x4220021F,
+ 0x021b0840, 0x0207017E,
+ 0x021b483c, 0x4201020C,
+ 0x021b4840, 0x01660172,
+ 0x021b0848, 0x4A4D4E4D,
+ 0x021b4848, 0x4A4F5049,
+ 0x021b0850, 0x3F3C3D31,
+ 0x021b4850, 0x3238372B,
+ 0x021b081c, 0x33333333,
+ 0x021b0820, 0x33333333,
+ 0x021b0824, 0x33333333,
+ 0x021b0828, 0x33333333,
+ 0x021b481c, 0x33333333,
+ 0x021b4820, 0x33333333,
+ 0x021b4824, 0x33333333,
+ 0x021b4828, 0x33333333,
+ 0x021b08b8, 0x00000800,
+ 0x021b48b8, 0x00000800,
+ 0x021b0004, 0x0002002D,
+ 0x021b0008, 0x00333030,
+ 0x021b000c, 0x3F435313,
+ 0x021b0010, 0xB66E8B63,
+ 0x021b0014, 0x01FF00DB,
+ 0x021b0018, 0x00001740,
+ 0x021b001c, 0x00008000,
+ 0x021b002c, 0x000026d2,
+ 0x021b0030, 0x00431023,
+ 0x021b0040, 0x00000027,
+ 0x021b0000, 0x831A0000,
+ 0x021b001c, 0x04008032,
+ 0x021b001c, 0x00008033,
+ 0x021b001c, 0x00048031,
+ 0x021b001c, 0x05208030,
+ 0x021b001c, 0x04008040,
+ 0x021b0020, 0x00005800,
+ 0x021b0818, 0x00011117,
+ 0x021b4818, 0x00011117,
+ 0x021b0004, 0x0002556D,
+ 0x021b0404, 0x00011006,
+ 0x021b001c, 0x00000000,
+};
+
+static void ddr_init(int *table, int size)
{
- struct mx6_ddr_sysinfo sysinfo = {
- /* width of data bus:0=16,1=32,2=64 */
- .dsize = mem_ddr.width/32,
- /* config for full 4GB range so that get_mem_size() works */
- .cs_density = 32, /* 32Gb per CS */
- /* single chip select */
- .ncs = 1,
- .cs1_mirror = 0,
- .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
-#ifdef RTT_NOM_120OHM
- .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
-#else
- .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
-#endif
- .walat = 1, /* Write additional latency */
- .ralat = 5, /* Read additional latency */
- .mif3_mode = 3, /* Command prediction working mode */
- .bi_on = 1, /* Bank interleaving enabled */
- .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
- .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
- };
+ int i;
- mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
- mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
+ for (i = 0; i < size / 2 ; i++)
+ writel(table[2 * i + 1], table[2 * i]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_mx6dq())
+ ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
+ else if (is_mx6dqp())
+ ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
+ else if (is_mx6sdl())
+ ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
}
void board_init_f(ulong dummy)
{
+ /* DDR initialization */
+ spl_dram_init();
+
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
- /* DDR initialization */
- spl_dram_init();
-
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
-
-void reset_cpu(ulong addr)
-{
-}
#endif
projects / people / ms / u-boot.git / blobdiff