mx6: ddr: Allow changing REFSEL and REFR fields

[people/ms/u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 5938c160af26631cc874936c48d6678866cc8791..32953aea2bb4b1ee4f83dfd5b296b00b23a0a5ad 100644 (file)
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -764,6 +764,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
        .sde_to_rst = 0,    /* LPDDR2 does not need this field */
        .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
        .ddr_type = DDR_TYPE_LPDDR2,
+       .refsel = 0,    /* Refresh cycles at 64KHz */
+       .refr = 3,      /* 4 refresh commands per refresh cycle */
 };
 
 #else
@@ -802,6 +804,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
        .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
        .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
        .ddr_type = DDR_TYPE_DDR3,
+       .refsel = 1,    /* Refresh cycles at 32KHz */
+       .refr = 7,      /* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {