mx6: ddr: Allow changing REFSEL and REFR fields

[people/ms/u-boot.git] / board / freescale / mx6ul_14x14_evk / mx6ul_14x14_evk.c

diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 88d3fbd9b19ff4019135baadf637bc083e6c2038..32953aea2bb4b1ee4f83dfd5b296b00b23a0a5ad 100644 (file)
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -60,13 +60,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
 
-#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |          \
-       PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)
-
 #define IOX_SDI IMX_GPIO_NR(5, 10)
 #define IOX_STCP IMX_GPIO_NR(5, 7)
 #define IOX_SHCP IMX_GPIO_NR(5, 11)
-#define IOX_OE IMX_GPIO_NR(5, 18)
+#define IOX_OE IMX_GPIO_NR(5, 8)
 
 static iomux_v3_cfg_t const iox_pads[] = {
        /* IOX_SDI */
@@ -117,7 +114,7 @@ static enum qn_level seq[3][2] = {
 
 static enum qn_func qn_output[8] = {
        qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset,
-       qn_disable, qn_enable
+       qn_disable, qn_disable
 };
 
 static void iox74lv_init(void)
@@ -154,8 +151,6 @@ static void iox74lv_init(void)
         * shift register will be output to pins
         */
        gpio_direction_output(IOX_STCP, 1);
-
-       gpio_direction_output(IOX_OE, 1);
 };
 
 #ifdef CONFIG_SYS_I2C_MXC
@@ -198,9 +193,7 @@ int power_init_board(void)
                       reg, rev_id);
 
                /* disable Low Power Mode during standby mode */
-               pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, &reg);
-               reg |= 0x1;
-               pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg);
+               pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1);
 
                /* SW1B step ramp up time from 2us to 4us/25mV */
                reg = 0x40;
@@ -282,18 +275,16 @@ static iomux_v3_cfg_t const usdhc2_pads[] = {
        MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
-static iomux_v3_cfg_t const usdhc2_cd_pads[] = {
-       /*
-        * The evk board uses DAT3 to detect CD card plugin,
-        * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
-        */
-       MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
-};
+/*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+       MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
 
-static iomux_v3_cfg_t const usdhc2_dat3_pads[] = {
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
        MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
-       MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL),
-};
+       MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
 #endif
 
 static void setup_iomux_uart(void)
@@ -305,7 +296,7 @@ static void setup_iomux_uart(void)
 
 #define QSPI_PAD_CTRL1 \
        (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
-        PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm)
+        PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
 
 static iomux_v3_cfg_t const quadspi_pads[] = {
        MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
@@ -356,8 +347,7 @@ int board_mmc_getcd(struct mmc *mmc)
 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
                ret = 1;
 #else
-               imx_iomux_v3_setup_multiple_pads(usdhc2_cd_pads,
-                                                ARRAY_SIZE(usdhc2_cd_pads));
+               imx_iomux_v3_setup_pad(usdhc2_cd_pad);
                gpio_direction_input(USDHC2_CD_GPIO);
 
                /*
@@ -366,8 +356,7 @@ int board_mmc_getcd(struct mmc *mmc)
                 */
                ret = gpio_get_value(USDHC2_CD_GPIO);
 
-               imx_iomux_v3_setup_multiple_pads(usdhc2_dat3_pads,
-                                                ARRAY_SIZE(usdhc2_dat3_pads));
+               imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
 #endif
                break;
        }
@@ -775,6 +764,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
        .sde_to_rst = 0,    /* LPDDR2 does not need this field */
        .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
        .ddr_type = DDR_TYPE_LPDDR2,
+       .refsel = 0,    /* Refresh cycles at 64KHz */
+       .refr = 3,      /* 4 refresh commands per refresh cycle */
 };
 
 #else
@@ -813,6 +804,8 @@ struct mx6_ddr_sysinfo ddr_sysinfo = {
        .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
        .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
        .ddr_type = DDR_TYPE_DDR3,
+       .refsel = 1,    /* Refresh cycles at 32KHz */
+       .refr = 7,      /* 8 refresh commands per refresh cycle */
 };
 
 static struct mx6_ddr3_cfg mem_ddr = {