mx6: ddr: Allow changing REFSEL and REFR fields

[people/ms/u-boot.git] / board / gateworks / gw_ventana / gw_ventana_spl.c

diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index d4418e554c4aac209a37126d4e6b73b009ea6c0c..b610e06f1de4dddfc964bceabac27276e8cba3a8 100644 (file)
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -15,6 +15,7 @@
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/mxc_i2c.h>
 #include <environment.h>
+#include <i2c.h>
 #include <spl.h>
 
 #include "gsc.h"
@@ -189,6 +190,20 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = {
        .trasmin = 3500,
 };
 
+/* MT41K512M16HA-125 (8Gb density) */
+static struct mx6_ddr3_cfg mt41k512m16ha_125 = {
+       .mem_speed = 1600,
+       .density = 8,
+       .width = 16,
+       .banks = 8,
+       .rowaddr = 16,
+       .coladdr = 10,
+       .pagesz = 2,
+       .trcd = 1375,
+       .trcmin = 4875,
+       .trasmin = 3500,
+};
+
 /*
  * calibration - these are the various CPU/DDR3 combinations we support
  */
@@ -340,6 +355,19 @@ static struct mx6_mmdc_calibration mx6dq_256x64_mmdc_calib = {
        .p1_mpwrdlctl = 0X40304239,
 };
 
+static struct mx6_mmdc_calibration mx6dq_512x32_mmdc_calib = {
+       /* write leveling calibration determine */
+       .p0_mpwldectrl0 = 0x002A0025,
+       .p0_mpwldectrl1 = 0x003A002A,
+       /* Read DQS Gating calibration */
+       .p0_mpdgctrl0 = 0x43430356,
+       .p0_mpdgctrl1 = 0x033C0335,
+       /* Read Calibration: DQS delay relative to DQ read access */
+       .p0_mprddlctl = 0x4B373F42,
+       /* Write Calibration: DQ/DM delay relative to DQS write access */
+       .p0_mpwrdlctl = 0x303E3C36,
+};
+
 static void spl_dram_init(int width, int size_mb, int board_model)
 {
        struct mx6_ddr3_cfg *mem = NULL;
@@ -365,6 +393,9 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
                .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
                .pd_fast_exit = 1, /* enable precharge power-down fast exit */
+               .ddr_type = DDR_TYPE_DDR3,
+               .refsel = 1,    /* Refresh cycles at 32KHz */
+               .refr = 7,      /* 8 refresh commands per refresh cycle */
        };
 
        /*
@@ -418,6 +449,11 @@ static void spl_dram_init(int width, int size_mb, int board_model)
                else
                        calib = &mx6sdl_256x32_mmdc_calib;
                debug("4gB density\n");
+       } else if (width == 32 && size_mb == 2048) {
+               mem = &mt41k512m16ha_125;
+               if (is_cpu_type(MXC_CPU_MX6Q))
+                       calib = &mx6dq_512x32_mmdc_calib;
+               debug("8gB density\n");
        } else if (width == 64 && size_mb == 512) {
                mem = &mt41k64m16jt_125;
                debug("1gB density\n");
@@ -525,9 +561,6 @@ void board_init_f(ulong dummy)
 
        /* Clear the BSS. */
        memset(__bss_start, 0, __bss_end - __bss_start);
-
-       /* disable boot watchdog */
-       gsc_boot_wd_disable();
 }
 
 /* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
@@ -559,7 +592,7 @@ void spl_board_init(void)
 /* return 1 if we wish to boot to uboot vs os (falcon mode) */
 int spl_start_uboot(void)
 {
-       int ret = 1;
+       unsigned char ret = 1;
 
        debug("%s\n", __func__);
 #ifdef CONFIG_SPL_ENV_SUPPORT
@@ -568,12 +601,15 @@ int spl_start_uboot(void)
        debug("boot_os=%s\n", getenv("boot_os"));
        if (getenv_yesno("boot_os") == 1)
                ret = 0;
+#else
+       /* use i2c-0:0x50:0x00 for falcon boot mode (0=linux, else uboot) */
+       i2c_set_bus_num(0);
+       gsc_i2c_read(0x50, 0x0, 1, &ret, 1);
 #endif
+       if (!ret)
+               gsc_boot_wd_disable();
+
        debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
        return ret;
 }
 #endif
-
-void reset_cpu(ulong addr)
-{
-}