Update ARM Integrator boards:

[people/ms/u-boot.git] / board / integratorap / integratorap.c

diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
index 31bd1d48eb58c83908f9b90fcac910c156ddb26a..4baf39a67780ee69d15b90005f557ea4b33f6932 100644 (file)
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -36,7 +36,7 @@
 #include <common.h>
 
 #ifdef CONFIG_PCI
-#   include <pci.h>
+#include <pci.h>
 #endif
 
 void flash__init (void);
@@ -46,7 +46,7 @@ void peripheral_power_enable (void);
 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
 void show_boot_progress(int progress)
 {
-    printf("Boot reached stage %d\n", progress);
+       printf("Boot reached stage %d\n", progress);
 }
 #endif
 
@@ -75,6 +75,11 @@ int board_init (void)
 
        gd->flags = 0;
 
+#ifdef CONFIG_CM_REMAP
+extern void cm_remap(void);
+       cm_remap();     /* remaps writeable memory to 0x00000000 */
+#endif
+
        icache_enable ();
 
        flash__init ();
@@ -475,6 +480,38 @@ void ether__init (void)
 ******************************/
 int dram_init (void)
 {
+       DECLARE_GLOBAL_DATA_PTR;
+
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+#ifdef CONFIG_CM_SPD_DETECT
+       {
+extern void dram_query(void);
+       unsigned long cm_reg_sdram;
+       unsigned long sdram_shift;
+
+       dram_query();   /* Assembler accesses to CM registers */
+                       /* Queries the SPD values             */
+
+       /* Obtain the SDRAM size from the CM SDRAM register */
+
+       cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
+       /*   Register         SDRAM size
+        *
+        *   0xXXXXXXbbb000bb    16 MB
+        *   0xXXXXXXbbb001bb    32 MB
+        *   0xXXXXXXbbb010bb    64 MB
+        *   0xXXXXXXbbb011bb   128 MB
+        *   0xXXXXXXbbb100bb   256 MB
+        *
+        */
+       sdram_shift              = ((cm_reg_sdram & 0x0000001C)/4)%4;
+       gd->bd->bi_dram[0].size  = 0x01000000 << sdram_shift;
+
+       }
+#endif /* CM_SPD_DETECT */
+
        return 0;
 }
 
@@ -612,3 +649,8 @@ ulong get_tbclk (void)
 {
        return CFG_HZ_CLOCK/div_clock;
 }
+
+/* The Integrator/AP timer1 is clocked at 24MHz
+ * can be divided by 16 or 256
+ * and is a 16-bit counter
+ */