#define FLASH29_REG_FIRST_CYCLE FLASH29_REG_ADRS (0x1555)
#define FLASH29_REG_SECOND_CYCLE FLASH29_REG_ADRS (0x2aaa)
-#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555)
+#define FLASH29_REG_THIRD_CYCLE FLASH29_REG_ADRS (0x3555)
#define FLASH29_REG_FOURTH_CYCLE FLASH29_REG_ADRS (0x4555)
#define FLASH29_REG_FIFTH_CYCLE FLASH29_REG_ADRS (0x5aaa)
#define FLASH29_REG_SIXTH_CYCLE FLASH29_REG_ADRS (0x6555)
#define FLASH29_CMD_CHIP_ERASE 0x80808080
#define FLASH29_CMD_READ_RESET 0xf0f0f0f0
#define FLASH29_CMD_AUTOSELECT 0x90909090
-#define FLASH29_CMD_READ 0x70707070
+#define FLASH29_CMD_READ 0x70707070
#define IN_RAM_CMD_READ 0x1
#define IN_RAM_CMD_WRITE 0x2
* can be relocated to scratch ram
*/
static void flash_read_cmd(int cmd, FPWV * pFA, char * string, int strLen)
-{
+{
int i,j;
- FPW temp,temp1;
+ FPW temp,temp1;
FPWV *str;
str = (FPWV *)string;
j= strLen/4;
-
+
if(cmd == FLASH29_CMD_AUTOSELECT)
{
- *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
- *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT;
- }
-
- if(cmd == FLASH29_CMD_READ)
- {
- i = 0;
- while(i<j)
- {
+ *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
+ *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_AUTOSELECT;
+ }
+
+ if(cmd == FLASH29_CMD_READ)
+ {
+ i = 0;
+ while(i<j)
+ {
temp = *pFA++;
temp1 = *(int *)0xa0000000;
- *(int *)0xbf0081f8 = temp1 + temp;
+ *(int *)0xbf0081f8 = temp1 + temp;
*str++ = temp;
i++;
- }
- }
-
- if(cmd == FLASH29_CMD_READ_RESET)
- {
- *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
- *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
- }
-
- *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
+ }
+ }
+
+ if(cmd == FLASH29_CMD_READ_RESET)
+ {
+ *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
+ *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
+ }
+
+ *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
}
/******************************************************************************
* can be relocated to scratch ram
*/
static void flash_write_cmd(int cmd, FPWV * pFA, FPW value)
-{
- *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
- *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
+{
+ *(FLASH29_REG_FIRST_CYCLE) = FLASH29_CMD_FIRST;
+ *(FLASH29_REG_SECOND_CYCLE) = FLASH29_CMD_SECOND;
if (cmd == FLASH29_CMD_SECTOR)
{
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
- *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
- *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
- *pFA = FLASH29_CMD_SECTOR;
- }
-
- if (cmd == FLASH29_CMD_SIXTH)
- {
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
- *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
- *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
- *(FLASH29_REG_SIXTH_CYCLE) = FLASH29_CMD_SIXTH;
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
+ *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+ *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
+ *pFA = FLASH29_CMD_SECTOR;
+ }
+
+ if (cmd == FLASH29_CMD_SIXTH)
+ {
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_CHIP_ERASE;
+ *(FLASH29_REG_FOURTH_CYCLE) = FLASH29_CMD_FOURTH;
+ *(FLASH29_REG_FIFTH_CYCLE) = FLASH29_CMD_FIFTH;
+ *(FLASH29_REG_SIXTH_CYCLE) = FLASH29_CMD_SIXTH;
}
- if (cmd == FLASH29_CMD_PROGRAM)
- {
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_PROGRAM;
+ if (cmd == FLASH29_CMD_PROGRAM)
+ {
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_PROGRAM;
*pFA = value;
- }
-
- if (cmd == FLASH29_CMD_READ_RESET)
- {
- *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
- }
-
- *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
+ }
+
+ if (cmd == FLASH29_CMD_READ_RESET)
+ {
+ *(FLASH29_REG_THIRD_CYCLE) = FLASH29_CMD_READ_RESET;
+ }
+
+ *(int *)0xbf0081f8 = *(int *)0xa0000000; /* dummy read switch back to sdram interface */
}
static void load_cmd(ulong cmd)
ulong *dst;
FUNCPTR_CP absEntry;
ulong func;
-
+
if (in_ram_cmd & cmd) return;
-
+
if (cmd == IN_RAM_CMD_READ)
{
func = (ulong)flash_read_cmd;
func = (ulong)flash_write_cmd;
}
- src = (ulong *)(func & 0xfffffff8);
- dst = (ulong *)0xbf008000;
- absEntry = (FUNCPTR_CP)(0xbf0081d0);
- absEntry(src,dst,0x38);
+ src = (ulong *)(func & 0xfffffff8);
+ dst = (ulong *)0xbf008000;
+ absEntry = (FUNCPTR_CP)(0xbf0081d0);
+ absEntry(src,dst,0x38);
- in_ram_cmd = cmd;
+ in_ram_cmd = cmd;
}
/*-----------------------------------------------------------------------
{
unsigned long size = 0;
int i;
-
- load_cmd(IN_RAM_CMD_READ);
+
+ load_cmd(IN_RAM_CMD_READ);
/* Init: no FLASHes known */
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
ulong flashbase = PHYS_FLASH_1;
ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
-
+
/* Disable write protection */
*buscon &= ~INCA_IP_EBU_EBU_BUSCON1_WRDIS;
memset(&flash_info[i], 0, sizeof(flash_info_t));
#endif
- flash_info[i].size =
+ flash_info[i].size =
flash_get_size((FPW *)flashbase, &flash_info[i]);
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n",
i, flash_info[i].size);
}
-
+
size += flash_info[i].size;
}
{
int i;
flash_info_t * info;
-
+
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
if (info->start[0] <= base && base < info->start[0] + info->size)
break;
}
-
+
return i == CFG_MAX_FLASH_BANKS ? 0 : info;
}
case FLASH_AM160B:
fmt = "29LV160B%s (16 Mbit, %s)\n";
break;
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
fmt = "28F800C3%s (8 Mbit, %s)\n";
break;
case FLASH_INTEL800B:
case FLASH_INTEL800T:
fmt = "28F800B3%s (8 Mbit, %s)\n";
break;
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
fmt = "28F160C3%s (16 Mbit, %s)\n";
break;
case FLASH_INTEL160B:
case FLASH_INTEL160T:
fmt = "28F160B3%s (16 Mbit, %s)\n";
break;
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
fmt = "28F320C3%s (32 Mbit, %s)\n";
break;
case FLASH_INTEL320B:
case FLASH_INTEL320T:
fmt = "28F320B3%s (32 Mbit, %s)\n";
break;
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
fmt = "28F640C3%s (64 Mbit, %s)\n";
break;
case FLASH_INTEL640B:
ulong flash_get_size (FPWV *addr, flash_info_t *info)
{
FUNCPTR_RD absEntry;
- FPW retValue;
+ FPW retValue;
int flag;
- load_cmd(IN_RAM_CMD_READ);
+ load_cmd(IN_RAM_CMD_READ);
absEntry = (FUNCPTR_RD)FLASH_READ_CMD;
flag = disable_interrupts();
absEntry(FLASH29_CMD_AUTOSELECT,0,0,0);
if (flag) enable_interrupts();
-
+
udelay(100);
flag = disable_interrupts();
int rcode = 0;
FUNCPTR_WR absEntry;
- load_cmd(IN_RAM_CMD_WRITE);
+ load_cmd(IN_RAM_CMD_WRITE);
absEntry = (FUNCPTR_WR)FLASH_WRITE_CMD;
if ((s_first < 0) || (s_first > s_last)) {
left > 0 && res == 0;
addr += sizeof(data), left -= sizeof(data) - bytes) {
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left )
data += *((uchar *)addr + i);
else
data += *src++;
projects / people / ms / u-boot.git / blobdiff