rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / cpu / mpc85xx / tlb.c

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index b319ad418b6d7b43c56b2418e287c1eb245cd6f8..a2d16ae2fa1017470c91363ea43b2fe7618a074a 100644 (file)
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -79,7 +79,6 @@ void invalidate_tlb(u8 tlb)
 
 void init_tlbs(void)
 {
-#ifdef CONFIG_FSL_INIT_TLBS
        int i;
 
        for (i = 0; i < num_tlb_entries; i++) {
@@ -88,8 +87,70 @@ void init_tlbs(void)
                        tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
                        tlb_table[i].iprot);
        }
-#endif
 
        return ;
 }
 
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+       unsigned int tlb_size;
+       unsigned int ram_tlb_index;
+       unsigned int ram_tlb_address;
+
+       /*
+        * Determine size of each TLB1 entry.
+        */
+       switch (memsize_in_meg) {
+       case 16:
+       case 32:
+               tlb_size = BOOKE_PAGESZ_16M;
+               break;
+       case 64:
+       case 128:
+               tlb_size = BOOKE_PAGESZ_64M;
+               break;
+       case 256:
+       case 512:
+               tlb_size = BOOKE_PAGESZ_256M;
+               break;
+       case 1024:
+       case 2048:
+               if (PVR_VER(get_pvr()) > PVR_VER(PVR_85xx))
+                       tlb_size = BOOKE_PAGESZ_1G;
+               else
+                       tlb_size = BOOKE_PAGESZ_256M;
+               break;
+       default:
+               puts("DDR: only 16M, 32M, 64M, 128M, 256M, 512M, 1G"
+                       " and 2G are supported.\n");
+
+               /*
+                * The memory was not able to be mapped.
+                * Default to a small size.
+                */
+               tlb_size = BOOKE_PAGESZ_64M;
+               memsize_in_meg = 64;
+               break;
+       }
+
+       /*
+        * Configure DDR TLB1 entries.
+        * Starting at TLB1 8, use no more than 8 TLB1 entries.
+        */
+       ram_tlb_index = 8;
+       ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+       while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
+             && ram_tlb_index < 16) {
+               set_tlb(1, ram_tlb_address, ram_tlb_address,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, ram_tlb_index, tlb_size, 1);
+
+               ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
+               ram_tlb_index++;
+       }
+
+       /*
+        * Confirm that the requested amount of memory was mapped.
+        */
+       return memsize_in_meg;
+}