Patch by Travis Sawyer, 30 Dec 2003:

[people/ms/u-boot.git] / cpu / ppc4xx / miiphy.c

diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index c5a90a9f21511a1d89b3f617a9f4a758bbf60f62..5ca66815c5e0f4c1cc92e7b4512d80a5eabc8bcf 100644 (file)
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -48,8 +48,8 @@
 #include <405_mal.h>
 #include <miiphy.h>
 
-#if defined(CONFIG_405GP) || defined(CONFIG_440) || defined(CONFIG_405EP)
-
+#if (defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined(CONFIG_440)) \
+   && !defined (CONFIG_NET_MULTI)
 
 /***********************************************************/
 /* Dump out to the screen PHY regs                         */
@@ -76,7 +76,6 @@ void miiphy_dump (unsigned char addr)
 } /* end dump */
 
 
-
 /***********************************************************/
 /* read a phy reg and return the value with a rc           */
 /***********************************************************/
@@ -94,7 +93,9 @@ int miiphy_read (unsigned char addr, unsigned char reg,
        while ((in32 (EMAC_STACR) & EMAC_STACR_OC) == 0) {
                udelay (7);
                if (i > 5) {
+#if 0  /* test-only */
                        printf ("read err 1\n");
+#endif
                        return -1;
                }
                i++;
@@ -102,6 +103,9 @@ int miiphy_read (unsigned char addr, unsigned char reg,
        sta_reg = reg;                          /* reg address */
        /* set clock (50Mhz) and read flags */
        sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+#ifdef CONFIG_PHY_CLK_FREQ
+       sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
+#endif
        sta_reg = sta_reg | (addr << 5);        /* Phy address */
 
        out32 (EMAC_STACR, sta_reg);
@@ -114,16 +118,20 @@ int miiphy_read (unsigned char addr, unsigned char reg,
        while ((sta_reg & EMAC_STACR_OC) == 0) {
                udelay (7);
                if (i > 5) {
+#if 0  /* test-only */
                        printf ("read err 2\n");
+#endif
                        return -1;
                }
                i++;
                sta_reg = in32 (EMAC_STACR);
        }
        if ((sta_reg & EMAC_STACR_PHYE) != 0) {
+#if 0  /* test-only */
                printf ("read err 3\n");
                printf ("a2: read: EMAC_STACR=0x%0lx, i=%d\n",
                        sta_reg, (int) i);      /* test-only */
+#endif
                return -1;
        }
 
@@ -157,6 +165,9 @@ int miiphy_write (unsigned char addr, unsigned char reg,
        sta_reg = reg;                          /* reg address */
        /* set clock (50Mhz) and read flags */
        sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+#ifdef CONFIG_PHY_CLK_FREQ
+       sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
+#endif
        sta_reg = sta_reg | ((unsigned long) addr << 5);        /* Phy address */
        memcpy (&sta_reg, &value, 2);   /* put in data */