clk: implement clk_set_defaults()

[people/ms/u-boot.git] / drivers / clk / clk-uclass.c

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index fbea72091b190c43fdf411a0d96f721735264faf..ad763795d9e8ef8912c08d5d4a8f8520caf1b3fd 100644 (file)
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -2,6 +2,7 @@
  * Copyright (C) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
  * Copyright (c) 2016, NVIDIA CORPORATION.
+ * Copyright (c) 2018, Theobroma Systems Design und Consulting GmbH
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
@@ -10,6 +11,7 @@
 #include <clk.h>
 #include <clk-uclass.h>
 #include <dm.h>
+#include <dm/read.h>
 #include <dt-structs.h>
 #include <errno.h>
 
@@ -53,7 +55,8 @@ static int clk_of_xlate_default(struct clk *clk,
        return 0;
 }
 
-int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
+static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
+                                  int index, struct clk *clk)
 {
        int ret;
        struct ofnode_phandle_args args;
@@ -65,7 +68,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
        assert(clk);
        clk->dev = NULL;
 
-       ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+       ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
                                         index, &args);
        if (ret) {
                debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
@@ -95,6 +98,127 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
 
        return clk_request(dev_clk, clk);
 }
+
+int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
+{
+       return clk_get_by_indexed_prop(dev, "clocks", index, clk);
+}
+
+static int clk_set_default_parents(struct udevice *dev)
+{
+       struct clk clk, parent_clk;
+       int index;
+       int num_parents;
+       int ret;
+
+       num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
+                                                 "#clock-cells");
+       if (num_parents < 0) {
+               debug("%s: could not read assigned-clock-parents for %p\n",
+                     __func__, dev);
+               return 0;
+       }
+
+       for (index = 0; index < num_parents; index++) {
+               ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
+                                             index, &parent_clk);
+               if (ret) {
+                       debug("%s: could not get parent clock %d for %s\n",
+                             __func__, index, dev_read_name(dev));
+                       return ret;
+               }
+
+               ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
+                                             index, &clk);
+               if (ret) {
+                       debug("%s: could not get assigned clock %d for %s\n",
+                             __func__, index, dev_read_name(dev));
+                       return ret;
+               }
+
+               ret = clk_set_parent(&clk, &parent_clk);
+
+               /*
+                * Not all drivers may support clock-reparenting (as of now).
+                * Ignore errors due to this.
+                */
+               if (ret == -ENOSYS)
+                       continue;
+
+               if (ret) {
+                       debug("%s: failed to reparent clock %d for %s\n",
+                             __func__, index, dev_read_name(dev));
+                       return ret;
+               }
+       }
+
+       return 0;
+}
+
+static int clk_set_default_rates(struct udevice *dev)
+{
+       struct clk clk;
+       int index;
+       int num_rates;
+       int size;
+       int ret = 0;
+       u32 *rates = NULL;
+
+       size = dev_read_size(dev, "assigned-clock-rates");
+       if (size < 0)
+               return 0;
+
+       num_rates = size / sizeof(u32);
+       rates = calloc(num_rates, sizeof(u32));
+       if (!rates)
+               return -ENOMEM;
+
+       ret = dev_read_u32_array(dev, "assigned-clock-rates", rates, num_rates);
+       if (ret)
+               goto fail;
+
+       for (index = 0; index < num_rates; index++) {
+               ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
+                                             index, &clk);
+               if (ret) {
+                       debug("%s: could not get assigned clock %d for %s\n",
+                             __func__, index, dev_read_name(dev));
+                       continue;
+               }
+
+               ret = clk_set_rate(&clk, rates[index]);
+               if (ret < 0) {
+                       debug("%s: failed to set rate on clock %d for %s\n",
+                             __func__, index, dev_read_name(dev));
+                       break;
+               }
+       }
+
+fail:
+       free(rates);
+       return ret;
+}
+
+int clk_set_defaults(struct udevice *dev)
+{
+       int ret;
+
+       /* If this is running pre-reloc state, don't take any action. */
+       if (!(gd->flags & GD_FLG_RELOC))
+               return 0;
+
+       debug("%s(%s)\n", __func__, dev_read_name(dev));
+
+       ret = clk_set_default_parents(dev);
+       if (ret)
+               return ret;
+
+       ret = clk_set_default_rates(dev);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
 # endif /* OF_PLATDATA */
 
 int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk)
@@ -188,6 +312,18 @@ ulong clk_set_rate(struct clk *clk, ulong rate)
        return ops->set_rate(clk, rate);
 }
 
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+       const struct clk_ops *ops = clk_dev_ops(clk->dev);
+
+       debug("%s(clk=%p, parent=%p)\n", __func__, clk, parent);
+
+       if (!ops->set_parent)
+               return -ENOSYS;
+
+       return ops->set_parent(clk, parent);
+}
+
 int clk_enable(struct clk *clk)
 {
        const struct clk_ops *ops = clk_dev_ops(clk->dev);