clk: renesas: Make PLL configurations per-SoC

[people/ms/u-boot.git] / drivers / clk / renesas / clk-rcar-gen3.c

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index d8576a33ae5561838620a37a7d8067ec682ef30b..76c6de2ab28dd8104035ed40fe98028a00812346 100644 (file)
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -74,56 +74,6 @@ static const u16 smstpcr[] = {
 /* Software Reset Clearing Register offsets */
 #define        SRSTCLR(i)      (0x940 + (i) * 4)
 
-/*
- * CPG Clock Data
- */
-
-/*
- *   MD                EXTAL           PLL0    PLL1    PLL2    PLL3    PLL4
- * 14 13 19 17 (MHz)
- *-------------------------------------------------------------------
- * 0  0  0  0  16.66 x 1       x180    x192    x144    x192    x144
- * 0  0  0  1  16.66 x 1       x180    x192    x144    x128    x144
- * 0  0  1  0  Prohibited setting
- * 0  0  1  1  16.66 x 1       x180    x192    x144    x192    x144
- * 0  1  0  0  20    x 1       x150    x160    x120    x160    x120
- * 0  1  0  1  20    x 1       x150    x160    x120    x106    x120
- * 0  1  1  0  Prohibited setting
- * 0  1  1  1  20    x 1       x150    x160    x120    x160    x120
- * 1  0  0  0  25    x 1       x120    x128    x96     x128    x96
- * 1  0  0  1  25    x 1       x120    x128    x96     x84     x96
- * 1  0  1  0  Prohibited setting
- * 1  0  1  1  25    x 1       x120    x128    x96     x128    x96
- * 1  1  0  0  33.33 / 2       x180    x192    x144    x192    x144
- * 1  1  0  1  33.33 / 2       x180    x192    x144    x128    x144
- * 1  1  1  0  Prohibited setting
- * 1  1  1  1  33.33 / 2       x180    x192    x144    x192    x144
- */
-#define CPG_PLL_CONFIG_INDEX(md)       ((((md) & BIT(14)) >> 11) | \
-                                        (((md) & BIT(13)) >> 11) | \
-                                        (((md) & BIT(19)) >> 18) | \
-                                        (((md) & BIT(17)) >> 17))
-
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
-       /* EXTAL div    PLL1 mult       PLL3 mult */
-       { 1,            192,            192,    },
-       { 1,            192,            128,    },
-       { 0, /* Prohibited setting */           },
-       { 1,            192,            192,    },
-       { 1,            160,            160,    },
-       { 1,            160,            106,    },
-       { 0, /* Prohibited setting */           },
-       { 1,            160,            160,    },
-       { 1,            128,            128,    },
-       { 1,            128,            84,     },
-       { 0, /* Prohibited setting */           },
-       { 1,            128,            128,    },
-       { 2,            192,            192,    },
-       { 2,            192,            128,    },
-       { 0, /* Prohibited setting */           },
-       { 2,            192,            192,    },
-};
-
 /*
  * SDn Clock
  */
@@ -192,7 +142,8 @@ static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
                return -EINVAL;
 
        for (i = 0; i < info->mod_clk_size; i++) {
-               if (info->mod_clk[i].id != MOD_CLK_ID(clkid))
+               if (info->mod_clk[i].id !=
+                   (info->mod_clk_base + MOD_CLK_PACK(clkid)))
                        continue;
 
                *mssr = &info->mod_clk[i];
@@ -322,6 +273,7 @@ static int gen3_clk_disable(struct clk *clk)
 static ulong gen3_clk_get_rate(struct clk *clk)
 {
        struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
+       struct cpg_mssr_info *info = priv->info;
        struct clk parent;
        const struct cpg_core_clk *core;
        const struct rcar_gen3_cpg_pll_config *pll_config =
@@ -350,14 +302,14 @@ static ulong gen3_clk_get_rate(struct clk *clk)
 
        switch (core->type) {
        case CLK_TYPE_IN:
-               if (core->id == CLK_EXTAL) {
+               if (core->id == info->clk_extal_id) {
                        rate = clk_get_rate(&priv->clk_extal);
                        debug("%s[%i] EXTAL clk: rate=%u\n",
                              __func__, __LINE__, rate);
                        return rate;
                }
 
-               if (core->id == CLK_EXTALR) {
+               if (core->id == info->clk_extalr_id) {
                        rate = clk_get_rate(&priv->clk_extalr);
                        debug("%s[%i] EXTALR clk: rate=%u\n",
                              __func__, __LINE__, rate);
@@ -518,7 +470,8 @@ int gen3_clk_probe(struct udevice *dev)
 
        cpg_mode = readl(rst_base + CPG_RST_MODEMR);
 
-       priv->cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+       priv->cpg_pll_config =
+               (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
        if (!priv->cpg_pll_config->extal_div)
                return -EINVAL;