mmc: omap_hsmmc: use a default 52MHz max clock rate if none is specified

[people/ms/u-boot.git] / drivers / mmc / omap_hsmmc.c

diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c
index e0b679aa2c5746f72aa0c3fb47e4ef114f83f620..caaa91460491a43868d31adc0d2eb2265242cbc2 100644 (file)
--- a/drivers/mmc/omap_hsmmc.c
+++ b/drivers/mmc/omap_hsmmc.c
@@ -93,7 +93,7 @@ struct omap_hsmmc_data {
        enum bus_mode mode;
 #endif
        u8 controller_flags;
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
        struct omap_hsmmc_adma_desc *adma_desc_table;
        uint desc_slot;
 #endif
@@ -117,7 +117,7 @@ struct omap_mmc_of_data {
        u8 controller_flags;
 };
 
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
 struct omap_hsmmc_adma_desc {
        u8 attr;
        u8 reserved;
@@ -741,7 +741,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc)
                        return -ETIMEDOUT;
                }
        }
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
        reg_val = readl(&mmc_base->hl_hwinfo);
        if (reg_val & MADMA_EN)
                priv->controller_flags |= OMAP_HSMMC_USE_ADMA;
@@ -834,7 +834,7 @@ static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
        }
 }
 
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
 static void omap_hsmmc_adma_desc(struct mmc *mmc, char *buf, u16 len, bool end)
 {
        struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc);
@@ -1037,7 +1037,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
                else
                        flags |= (DP_DATA | DDIR_WRITE);
 
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
                if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) &&
                    !mmc_is_tuning_cmd(cmd->cmdidx)) {
                        omap_hsmmc_prepare_data(mmc, data);
@@ -1082,7 +1082,7 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
                }
        }
 
-#ifndef CONFIG_OMAP34XX
+#ifdef CONFIG_MMC_OMAP_HS_ADMA
        if ((priv->controller_flags & OMAP_HSMMC_USE_ADMA) && data &&
            !mmc_is_tuning_cmd(cmd->cmdidx)) {
                u32 sz_mb, timeout;
@@ -1181,8 +1181,9 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
        return 0;
 }
 
+#if CONFIG_IS_ENABLED(MMC_WRITE)
 static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
-                               unsigned int size)
+                         unsigned int size)
 {
        unsigned int *input_buf = (unsigned int *)buf;
        unsigned int mmc_stat;
@@ -1235,7 +1236,13 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
        }
        return 0;
 }
-
+#else
+static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
+                         unsigned int size)
+{
+       return -ENOTSUPP;
+}
+#endif
 static void omap_hsmmc_stop_clock(struct hsmmc *mmc_base)
 {
        writel(readl(&mmc_base->sysctl) & ~CEN_ENABLE, &mmc_base->sysctl);
@@ -1825,6 +1832,8 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev)
        if (ret < 0)
                return ret;
 
+       if (!cfg->f_max)
+               cfg->f_max = 52000000;
        cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
        cfg->f_min = 400000;
        cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;