net: designware: add clock support

[people/ms/u-boot.git] / drivers / net / designware.h

diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index afeaccec19a4858ecc61d26834fb2d2478656ef5..252cd24f1aafbc46b0d030fc3e6a4a37e9736869 100644 (file)
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -8,6 +8,10 @@
 #ifndef _DW_ETH_H
 #define _DW_ETH_H
 
+#ifdef CONFIG_DM_GPIO
+#include <asm-generic/gpio.h>
+#endif
+
 #define CONFIG_TX_DESCR_NUM    16
 #define CONFIG_RX_DESCR_NUM    16
 #define CONFIG_ETH_BUFSIZE     2048
@@ -68,7 +72,9 @@ struct eth_dma_regs {
        u32 status;             /* 0x14 */
        u32 opmode;             /* 0x18 */
        u32 intenable;          /* 0x1c */
-       u8 reserved[40];
+       u32 reserved1[2];
+       u32 axibus;             /* 0x28 */
+       u32 reserved2[7];
        u32 currhosttxdesc;     /* 0x48 */
        u32 currhostrxdesc;     /* 0x4c */
        u32 currhosttxbuffaddr; /* 0x50 */
@@ -77,18 +83,18 @@ struct eth_dma_regs {
 
 #define DW_DMA_BASE_OFFSET     (0x1000)
 
+/* Default DMA Burst length */
+#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
+#endif
+
 /* Bus mode register definitions */
 #define FIXEDBURST             (1 << 16)
 #define PRIORXTX_41            (3 << 14)
 #define PRIORXTX_31            (2 << 14)
 #define PRIORXTX_21            (1 << 14)
 #define PRIORXTX_11            (0 << 14)
-#define BURST_1                        (1 << 8)
-#define BURST_2                        (2 << 8)
-#define BURST_4                        (4 << 8)
-#define BURST_8                        (8 << 8)
-#define BURST_16               (16 << 8)
-#define BURST_32               (32 << 8)
+#define DMA_PBL                        (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
 #define RXHIGHPRIO             (1 << 1)
 #define DMAMAC_SRST            (1 << 0)
 
@@ -108,9 +114,9 @@ struct eth_dma_regs {
 struct dmamacdescr {
        u32 txrx_status;
        u32 dmamac_cntl;
-       void *dmamac_addr;
-       struct dmamacdescr *dmamac_next;
-} __aligned(16);
+       u32 dmamac_addr;
+       u32 dmamac_next;
+} __aligned(ARCH_DMA_MINALIGN);
 
 /*
  * txrx_status definitions
@@ -215,22 +221,51 @@ struct dmamacdescr {
 #endif
 
 struct dw_eth_dev {
-       u32 interface;
-       u32 tx_currdescnum;
-       u32 rx_currdescnum;
-
        struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
        struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+       char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+       char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 
-       char txbuffs[TX_TOTAL_BUFSIZE];
-       char rxbuffs[RX_TOTAL_BUFSIZE];
+       u32 interface;
+       u32 max_speed;
+       u32 tx_currdescnum;
+       u32 rx_currdescnum;
 
        struct eth_mac_regs *mac_regs_p;
        struct eth_dma_regs *dma_regs_p;
-
+#ifndef CONFIG_DM_ETH
        struct eth_device *dev;
+#endif
+#ifdef CONFIG_DM_GPIO
+       struct gpio_desc reset_gpio;
+#endif
+#ifdef CONFIG_CLK
+       struct clk *clocks;     /* clock list */
+       int clock_count;        /* number of clock in clock list */
+#endif
+
        struct phy_device *phydev;
        struct mii_dev *bus;
 };
 
+#ifdef CONFIG_DM_ETH
+int designware_eth_ofdata_to_platdata(struct udevice *dev);
+int designware_eth_probe(struct udevice *dev);
+extern const struct eth_ops designware_eth_ops;
+
+struct dw_eth_pdata {
+       struct eth_pdata eth_pdata;
+       u32 reset_delays[3];
+};
+
+int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr);
+int designware_eth_enable(struct dw_eth_dev *priv);
+int designware_eth_send(struct udevice *dev, void *packet, int length);
+int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp);
+int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
+                                  int length);
+void designware_eth_stop(struct udevice *dev);
+int designware_eth_write_hwaddr(struct udevice *dev);
+#endif
+
 #endif