pci: Fix decode regions for memory banks

[people/ms/u-boot.git] / drivers / pci / pci-uclass.c

diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index b36ef3338ceb84d7c2ffbbfb39d0925e3532c2a6..ad43e8a27cc12404a0b198ece82e0dd8760ea75b 100644 (file)
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -518,6 +518,64 @@ int pci_auto_config_devices(struct udevice *bus)
        return sub_bus;
 }
 
+int pci_generic_mmap_write_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong value,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0)
+               return 0;
+
+       switch (size) {
+       case PCI_SIZE_8:
+               writeb(value, address);
+               return 0;
+       case PCI_SIZE_16:
+               writew(value, address);
+               return 0;
+       case PCI_SIZE_32:
+               writel(value, address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
+int pci_generic_mmap_read_config(
+       struct udevice *bus,
+       int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
+       pci_dev_t bdf,
+       uint offset,
+       ulong *valuep,
+       enum pci_size_t size)
+{
+       void *address;
+
+       if (addr_f(bus, bdf, offset, &address) < 0) {
+               *valuep = pci_get_ff(size);
+               return 0;
+       }
+
+       switch (size) {
+       case PCI_SIZE_8:
+               *valuep = readb(address);
+               return 0;
+       case PCI_SIZE_16:
+               *valuep = readw(address);
+               return 0;
+       case PCI_SIZE_32:
+               *valuep = readl(address);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 int dm_pci_hose_probe_bus(struct udevice *bus)
 {
        int sub_bus;
@@ -757,18 +815,17 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
                          ofnode node)
 {
        int pci_addr_cells, addr_cells, size_cells;
-       phys_addr_t base = 0, size;
        int cells_per_record;
        const u32 *prop;
        int len;
        int i;
 
-       prop = ofnode_read_prop(node, "ranges", &len);
+       prop = ofnode_get_property(node, "ranges", &len);
        if (!prop)
                return -EINVAL;
-       pci_addr_cells = ofnode_read_addr_cells(node);
-       addr_cells = ofnode_read_addr_cells(parent_node);
-       size_cells = ofnode_read_size_cells(node);
+       pci_addr_cells = ofnode_read_simple_addr_cells(node);
+       addr_cells = ofnode_read_simple_addr_cells(parent_node);
+       size_cells = ofnode_read_simple_size_cells(node);
 
        /* PCI addresses are always 3-cells */
        len /= sizeof(u32);
@@ -816,6 +873,21 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
        }
 
        /* Add a region for our local memory */
+#ifdef CONFIG_NR_DRAM_BANKS
+       bd_t *bd = gd->bd;
+
+       for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
+               if (bd->bi_dram[i].size) {
+                       pci_set_region(hose->regions + hose->region_count++,
+                                      bd->bi_dram[i].start,
+                                      bd->bi_dram[i].start,
+                                      bd->bi_dram[i].size,
+                                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+               }
+       }
+#else
+       phys_addr_t base = 0, size;
+
        size = gd->ram_size;
 #ifdef CONFIG_SYS_SDRAM_BASE
        base = CONFIG_SYS_SDRAM_BASE;
@@ -824,6 +896,7 @@ static int decode_regions(struct pci_controller *hose, ofnode parent_node,
                size = gd->pci_ram_top - base;
        pci_set_region(hose->regions + hose->region_count++, base, base,
                       size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+#endif
 
        return 0;
 }