Merge git://www.denx.de/git/u-boot-imx

[people/ms/u-boot.git] / drivers / pci / pcie_layerscape.c

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index b6806cf67b69bae3f5babaf5a94ffe8d88949fbc..610f85c4e8ea464edc531ba4af4fa252d5b24044 100644 (file)
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  * Layerscape PCIe driver
  *
@@ -12,6 +13,10 @@
 #include <errno.h>
 #include <malloc.h>
 #include <dm.h>
+#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
+       defined(CONFIG_ARM)
+#include <asm/arch/clock.h>
+#endif
 #include "pcie_layerscape.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -167,6 +172,28 @@ static void ls_pcie_setup_atu(struct ls_pcie *pcie)
        pci_get_regions(pcie->bus, &io, &mem, &pref);
        idx = PCIE_ATU_REGION_INDEX1 + 1;
 
+       /* Fix the pcie memory map for LS2088A series SoCs */
+       svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+       if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+           svr == SVR_LS2048A || svr == SVR_LS2044A ||
+           svr == SVR_LS2081A || svr == SVR_LS2041A) {
+               if (io)
+                       io->phys_start = (io->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               if (mem)
+                       mem->phys_start = (mem->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               if (pref)
+                       pref->phys_start = (pref->phys_start &
+                                        (PCIE_PHYS_SIZE - 1)) +
+                                        LS2088A_PCIE1_PHYS_ADDR +
+                                        LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+       }
+
        if (io)
                /* ATU : OUTBOUND : IO */
                ls_pcie_atu_outbound_set(pcie, idx++,
@@ -409,6 +436,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
        ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
 }
 
+static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie)
+{
+       ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
+}
+
 static void ls_pcie_setup_ep(struct ls_pcie *pcie)
 {
        u32 sriov;
@@ -432,6 +464,8 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie)
                ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
                ls_pcie_ep_setup_atu(pcie);
        }
+
+       ls_pcie_ep_enable_cfg(pcie);
 }
 
 static int ls_pcie_probe(struct udevice *dev)
@@ -442,7 +476,9 @@ static int ls_pcie_probe(struct udevice *dev)
        u8 header_type;
        u16 link_sta;
        bool ep_mode;
+       uint svr;
        int ret;
+       fdt_size_t cfg_size;
 
        pcie->bus = dev;
 
@@ -495,6 +531,22 @@ static int ls_pcie_probe(struct udevice *dev)
                return ret;
        }
 
+       /*
+        * Fix the pcie memory map address and PF control registers address
+        * for LS2088A series SoCs
+        */
+       svr = get_svr();
+       svr = (svr >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+       if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+           svr == SVR_LS2048A || svr == SVR_LS2044A ||
+           svr == SVR_LS2081A || svr == SVR_LS2041A) {
+               cfg_size = fdt_resource_size(&pcie->cfg_res);
+               pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR +
+                                       LS2088A_PCIE_PHYS_SIZE * pcie->idx;
+               pcie->cfg_res.end = pcie->cfg_res.start + cfg_size;
+               pcie->ctrl = pcie->lut + 0x40000;
+       }
+
        pcie->cfg0 = map_physmem(pcie->cfg_res.start,
                                 fdt_resource_size(&pcie->cfg_res),
                                 MAP_NOCACHE);