powerpc/85xx: Update default hwconfig on P1022DS

[people/ms/u-boot.git] / include / configs / P1022DS.h

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 2b8fc7deca2c0469ef7abaabaf96b2d85084a317..fb2a41ce240aba43b02ecae399c8402f97204cbd 100644 (file)
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -14,6 +14,10 @@
 
 #include "../board/freescale/common/ics307_clk.h"
 
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE                   /* BOOKE */
 #define CONFIG_E500                    /* BOOKE e500 family */
@@ -26,6 +30,10 @@
 #define CONFIG_SYS_TEXT_BASE   0xeff80000
 #endif
 
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS    0xeffffffc
+#endif
+
 #define CONFIG_FSL_ELBC                        /* Has Enhanced localbus controller */
 #define CONFIG_PCI                     /* Enable PCI/PCIE */
 #define CONFIG_PCIE1                   /* PCIE controler 1 (slot 1) */
@@ -35,10 +43,11 @@
 #define CONFIG_FSL_PCIE_RESET          /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT           /* enable 64-bit PCI resources */
 
-#define CONFIG_PHYS_64BIT
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_ENABLE_36BIT_PHYS
 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP                16      /* number of TLB1 entries */
+#endif
 
 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
 
@@ -61,7 +70,11 @@
  */
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000      /* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR             0xffe00000      /* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_CCSRBAR_PHYS                0xfffe00000ull
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR
+#endif
 #define CONFIG_SYS_IMMR                        CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
@@ -83,7 +96,7 @@
 
 /* I2C addresses of SPD EEPROMs */
 #define CONFIG_SYS_SPD_BUS_NUM         1
-#define SPD_EEPROM_ADDRESS1            0x51    /* CTLR 0 DIMM 0 */
+#define SPD_EEPROM_ADDRESS             0x51    /* CTLR 0 DIMM 0 */
 
 /*
  * Memory map
@@ -107,7 +120,11 @@
  * Local Bus Definitions
  */
 #define CONFIG_SYS_FLASH_BASE          0xe0000000 /* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_FLASH_BASE_PHYS     0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS     CONFIG_SYS_FLASH_BASE
+#endif
 
 #define CONFIG_FLASH_BR_PRELIM  \
        (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
@@ -141,13 +158,17 @@
 
 #define CONFIG_FSL_NGPIXIS
 #define PIXIS_BASE             0xffdf0000      /* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
 #define PIXIS_BASE_PHYS                0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS                PIXIS_BASE
+#endif
 
 #define CONFIG_SYS_BR2_PRELIM  (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
 #define CONFIG_SYS_OR2_PRELIM  (OR_AM_32KB | 0x6ff7)
 
 #define PIXIS_LBMAP_SWITCH     7
-#define PIXIS_LBMAP_MASK       0xE0
+#define PIXIS_LBMAP_MASK       0xF0
 #define PIXIS_LBMAP_ALTBANK    0x20
 
 #define CONFIG_SYS_INIT_RAM_LOCK
@@ -181,13 +202,12 @@
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /* Video */
-#undef CONFIG_FSL_DIU_FB
-
 #ifdef CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_DIU_ADDR    (CONFIG_SYS_CCSRBAR + 0x10000)
 #define CONFIG_VIDEO
 #define CONFIG_CMD_BMP
 #define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
 #define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
@@ -199,6 +219,22 @@
 #undef CONFIG_SYS_FLASH_EMPTY_INFO
 #endif
 
+#ifndef CONFIG_DIU
+#define CONFIG_ATI
+#endif
+
+#ifdef CONFIG_ATI
+#define VIDEO_IO_OFFSET                CONFIG_SYS_PCIE1_IO_VIRT
+#define CONFIG_VIDEO
+#define CONFIG_BIOSEMU
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
 /*
  * Pass open firmware flat tree
  */
@@ -237,32 +273,59 @@
 
 /* controller 1, Slot 2, tgtid 1, Base address a000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT      0xc0000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS      0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xc0000000
+#endif
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT       0xffc20000
 #define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xffc20000
+#endif
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT      0xa0000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS      0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xa0000000
+#endif
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT       0xffc10000
 #define CONFIG_SYS_PCIE2_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xffc10000
+#endif
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00010000      /* 64k */
 
 /* controller 3, Slot 1, tgtid 3, Base address b000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT      0x80000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_MEM_BUS       0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS      0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS       0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS      0x80000000
+#endif
 #define CONFIG_SYS_PCIE3_MEM_SIZE      0x20000000      /* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT       0xffc00000
 #define CONFIG_SYS_PCIE3_IO_BUS                0x00000000
+#ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_PCIE3_IO_PHYS       0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS       0xffc00000
+#endif
 #define CONFIG_SYS_PCIE3_IO_SIZE       0x00010000      /* 64k */
 
 #ifdef CONFIG_PCI
@@ -275,6 +338,7 @@
 /* SATA */
 #define CONFIG_LIBATA
 #define CONFIG_FSL_SATA
+#define CONFIG_FSL_SATA_V2
 
 #define CONFIG_SYS_SATA_MAX_DEVICE     2
 #define CONFIG_SATA1
@@ -444,6 +508,7 @@
        "dium=mw e002c01c\0"                                            \
        "diuerr=md e002c014 1\0"                                        \
        "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
+       "hwconfig=esdhc;audclk:12\0"                                    \
        "monitor=0-DVI\0"
 
 #define CONFIG_HDBOOT                                  \