configs: Migrate RBTREE, LZO, CMD_MTDPARTS, CMD_UBI and CMD_UBIFS

[people/ms/u-boot.git] / include / configs / T208xQDS.h

diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 742174f60d0c667f608cfb4442c5e94cd87a487a..4fce859073516ef140c1fb768a97665907674a8c 100644 (file)
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -11,24 +11,16 @@
 #ifndef __T208xQDS_H
 #define __T208xQDS_H
 
-#define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
-#define CONFIG_MMC
-#define CONFIG_USB_EHCI
-#if defined(CONFIG_PPC_T2080)
-#define CONFIG_T2080QDS
+#if defined(CONFIG_ARCH_T2080)
 #define CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SRIO                /* Enable Serial RapidIO Support */
 #define CONFIG_SRIO1           /* SRIO port 1 */
 #define CONFIG_SRIO2           /* SRIO port 2 */
-#elif defined(CONFIG_PPC_T2081)
-#define CONFIG_T2081QDS
+#elif defined(CONFIG_ARCH_T2081)
 #endif
 
 /* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500            /* BOOKE e500 family */
-#define CONFIG_E500MC          /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV   /* Category E.HV supported */
 #define CONFIG_MP              /* support multiple processors */
 #define CONFIG_ENABLE_36BIT_PHYS
@@ -39,23 +31,14 @@
 #endif
 
 #define CONFIG_SYS_FSL_CPC     /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC     CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_IFC         /* Enable IFC Support */
-#define CONFIG_FSL_CAAM                /* Enable SEC/CAAM */
-#define CONFIG_FSL_LAW         /* Use common FSL init code */
+#define CONFIG_SYS_NUM_CPC     CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_ENV_OVERWRITE
 
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
-#if defined(CONFIG_PPC_T2080)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
-#elif defined(CONFIG_PPC_T2081)
-#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
-#endif
 
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x00201000
 #define CONFIG_SPL_TEXT_BASE           0xFFFD8000
 #define CONFIG_SPL_PAD_TO              0x40000
@@ -66,7 +49,6 @@
 #define CONFIG_SPL_SKIP_RELOCATE
 #define CONFIG_SPL_COMMON_INIT_DDR
 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#define CONFIG_SYS_NO_FLASH
 #endif
 
 #ifdef CONFIG_NAND
@@ -75,13 +57,16 @@
 #define CONFIG_SYS_NAND_U_BOOT_START   0x00200000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 << 10)
 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg
+#endif
 #define CONFIG_SPL_NAND_BOOT
 #endif
 
 #ifdef CONFIG_SPIFLASH
 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
-#define CONFIG_SPL_SPI_SUPPORT
-#define CONFIG_SPL_SPI_FLASH_SUPPORT
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
@@ -91,6 +76,11 @@
 #ifndef CONFIG_SPL_BUILD
 #define        CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg
+#endif
 #define CONFIG_SPL_SPI_BOOT
 #endif
 
@@ -105,6 +95,11 @@
 #ifndef CONFIG_SPL_BUILD
 #define        CONFIG_SYS_MPC85XX_NO_RESETVEC
 #endif
+#if defined(CONFIG_ARCH_T2080)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg
+#elif defined(CONFIG_ARCH_T2081)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg
+#endif
 #define CONFIG_SPL_MMC_BOOT
 #endif
 
@@ -117,7 +112,6 @@
 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
                (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
-#define CONFIG_SYS_NO_FLASH
 #endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
@@ -139,7 +133,7 @@
 #define CONFIG_MEM_INIT_VALUE          0xdeadbeef
 #endif
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
@@ -221,7 +215,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 #define CONFIG_DDR_SPD
-#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SYS_SPD_BUS_NUM 0
 #define CONFIG_SYS_SDRAM_SIZE  2048    /* for fixed parameter use */
@@ -543,7 +536,6 @@ unsigned long get_board_ddr_clk(void);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_PCI             /* Enable PCI/PCIE */
 #define CONFIG_PCIE1           /* PCIE controller 1 */
 #define CONFIG_PCIE2           /* PCIE controller 2 */
 #define CONFIG_PCIE3           /* PCIE controller 3 */
@@ -593,9 +585,7 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_FSL_PCIE_RESET     /* need PCIe reset errata */
-#define CONFIG_PCI_PNP         /* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
 #endif
 
 /* Qman/Bman */
@@ -705,14 +695,12 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SATA2               CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS         FLAGS_DMA
 #define CONFIG_LBA48
-#define CONFIG_CMD_SATA
-#define CONFIG_DOS_PARTITION
 #endif
 
 /*
  * USB
  */
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_HAS_FSL_DR_USB
@@ -727,18 +715,15 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_DOS_PARTITION
 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 #endif
 
 /*
  * Dynamic MTD Partition support with mtdparts
  */
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
-#define CONFIG_CMD_MTDPARTS
 #define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
                        "spi0=spife110000.0"
@@ -757,20 +742,12 @@ unsigned long get_board_ddr_clk(void);
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ERRATA
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_REGINFO
 
 #ifdef CONFIG_PCI
 #define CONFIG_CMD_PCI
 #endif
 
-/* Hash command with SHA acceleration supported in hardware */
-#ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
-#define CONFIG_SHA_HW_ACCEL
-#endif
-
 /*
  * Miscellaneous configurable options
  */
@@ -809,7 +786,6 @@ unsigned long get_board_ddr_clk(void);
 
 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR                1000000
-#define CONFIG_BAUDRATE                115200
 #define __USB_PHY_TYPE         utmi
 
 #define        CONFIG_EXTRA_ENV_SETTINGS                               \