* Code cleanup:

[people/ms/u-boot.git] / include / configs / TQM8260.h

diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h
index 1ea9a5e162e52566058bcdcca40cf7ae51f5c8bb..2961a6a76b3e69430c3be7fefd5ca4cf9af2f199 100644 (file)
--- a/include/configs/TQM8260.h
+++ b/include/configs/TQM8260.h
@@ -394,7 +394,7 @@
  * HID1 has only read-only information - nothing to set.
  */
 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
-                                HID0_IFEM|HID0_ABE)
+                               HID0_IFEM|HID0_ABE)
 #define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 #define CFG_HID2        0
 
@@ -436,10 +436,10 @@
  */
 #if defined(CONFIG_WATCHDOG)
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+                        SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 #else
 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
-                         SYPCR_SWRI|SYPCR_SWP)
+                        SYPCR_SWRI|SYPCR_SWP)
 #endif /* CONFIG_WATCHDOG */
 
 /*-----------------------------------------------------------------------
@@ -517,16 +517,16 @@
 /* Bank 0 - FLASH
  */
 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_GPCM_P                  |\
-                         BRx_V)
+                        BRx_PS_64                      |\
+                        BRx_MS_GPCM_P                  |\
+                        BRx_V)
 
 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
-                         ORxG_CSNT                      |\
-                         ORxG_ACS_DIV1                  |\
-                         ORxG_SCY_3_CLK                 |\
-                         ORxG_EHTR                      |\
-                         ORxG_TRLX)
+                        ORxG_CSNT                      |\
+                        ORxG_ACS_DIV1                  |\
+                        ORxG_SCY_3_CLK                 |\
+                        ORxG_EHTR                      |\
+                        ORxG_TRLX)
 
        /* SDRAM on TQM8260 can have either 8 or 9 columns.
         * The number affects configuration values.
@@ -538,9 +538,9 @@
 #define CFG_LSRT        0x20
 #ifndef CFG_RAMBOOT
 #define CFG_BR1_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
-                         BRx_PS_64                      |\
-                         BRx_MS_SDRAM_P                 |\
-                         BRx_V)
+                        BRx_PS_64                      |\
+                        BRx_MS_SDRAM_P                 |\
+                        BRx_V)
 
 #define CFG_OR1_PRELIM CFG_OR1_8COL
 
@@ -548,48 +548,48 @@
        /* SDRAM initialization values for 8-column chips
         */
 #define CFG_OR1_8COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A7             |\
-                         ORxS_NUMR_12)
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI1_A7             |\
+                        ORxS_NUMR_12)
 
 #define CFG_PSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+                        PSDMR_SDAM_A15_IS_A5           |\
+                        PSDMR_BSMA_A12_A14             |\
+                        PSDMR_SDA10_PBI1_A8            |\
+                        PSDMR_RFRC_7_CLK               |\
+                        PSDMR_PRETOACT_2W              |\
+                        PSDMR_ACTTORW_2W               |\
+                        PSDMR_LDOTOPRE_1C              |\
+                        PSDMR_WRC_2C                   |\
+                        PSDMR_EAMUX                    |\
+                        PSDMR_CL_2)
 
        /* SDRAM initialization values for 9-column chips
         */
 #define CFG_OR1_9COL    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A5             |\
-                         ORxS_NUMR_13)
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI1_A5             |\
+                        ORxS_NUMR_13)
 
 #define CFG_PSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A12_A14             |\
-                         PSDMR_SDA10_PBI1_A7            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_EAMUX                    |\
-                         PSDMR_CL_2)
+                        PSDMR_SDAM_A16_IS_A5           |\
+                        PSDMR_BSMA_A12_A14             |\
+                        PSDMR_SDA10_PBI1_A7            |\
+                        PSDMR_RFRC_7_CLK               |\
+                        PSDMR_PRETOACT_2W              |\
+                        PSDMR_ACTTORW_2W               |\
+                        PSDMR_LDOTOPRE_1C              |\
+                        PSDMR_WRC_2C                   |\
+                        PSDMR_EAMUX                    |\
+                        PSDMR_CL_2)
 
 /* Bank 2 - Local bus SDRAM
  */
 #ifdef CFG_INIT_LOCAL_SDRAM
 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
-                         BRx_PS_32                      |\
-                         BRx_MS_SDRAM_L                 |\
-                         BRx_V)
+                        BRx_PS_32                      |\
+                        BRx_MS_SDRAM_L                 |\
+                        BRx_V)
 
 #define CFG_OR2_PRELIM CFG_OR2_8COL
 
@@ -598,40 +598,40 @@
        /* SDRAM initialization values for 8-column chips
         */
 #define CFG_OR2_8COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A8             |\
-                         ORxS_NUMR_12)
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI1_A8             |\
+                        ORxS_NUMR_12)
 
 #define CFG_LSDMR_8COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A15_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A9            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+                        PSDMR_SDAM_A15_IS_A5           |\
+                        PSDMR_BSMA_A13_A15             |\
+                        PSDMR_SDA10_PBI1_A9            |\
+                        PSDMR_RFRC_7_CLK               |\
+                        PSDMR_PRETOACT_2W              |\
+                        PSDMR_ACTTORW_2W               |\
+                        PSDMR_BL                       |\
+                        PSDMR_LDOTOPRE_1C              |\
+                        PSDMR_WRC_2C                   |\
+                        PSDMR_CL_2)
 
        /* SDRAM initialization values for 9-column chips
         */
 #define CFG_OR2_9COL    ((~(CFG_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
-                         ORxS_BPD_4                     |\
-                         ORxS_ROWST_PBI1_A6             |\
-                         ORxS_NUMR_13)
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI1_A6             |\
+                        ORxS_NUMR_13)
 
 #define CFG_LSDMR_9COL  (PSDMR_PBI                      |\
-                         PSDMR_SDAM_A16_IS_A5           |\
-                         PSDMR_BSMA_A13_A15             |\
-                         PSDMR_SDA10_PBI1_A8            |\
-                         PSDMR_RFRC_7_CLK               |\
-                         PSDMR_PRETOACT_2W              |\
-                         PSDMR_ACTTORW_2W               |\
-                         PSDMR_BL                       |\
-                         PSDMR_LDOTOPRE_1C              |\
-                         PSDMR_WRC_2C                   |\
-                         PSDMR_CL_2)
+                        PSDMR_SDAM_A16_IS_A5           |\
+                        PSDMR_BSMA_A13_A15             |\
+                        PSDMR_SDA10_PBI1_A8            |\
+                        PSDMR_RFRC_7_CLK               |\
+                        PSDMR_PRETOACT_2W              |\
+                        PSDMR_ACTTORW_2W               |\
+                        PSDMR_BL                       |\
+                        PSDMR_LDOTOPRE_1C              |\
+                        PSDMR_WRC_2C                   |\
+                        PSDMR_CL_2)
 
 #endif /* CFG_INIT_LOCAL_SDRAM */