drivers, block: remove sil680 driver

[people/ms/u-boot.git] / include / configs / iocon.h

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 79c4736bc5df949fc39cb9f667eddd11ccd59744..99e920b46a1fae7594d011b5ae06dd4852f4e511 100644 (file)
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -17,10 +17,11 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME                iocon
-#define CONFIG_IDENT_STRING    " iocon 0.05"
 #include "amcc-common.h"
 
-#define CONFIG_BOARD_EARLY_INIT_F
+/* Reclaim some space. */
+#undef CONFIG_SYS_LONGHELP
+
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
 
@@ -32,14 +33,6 @@
 #define PLLMR0_DEFAULT PLLMR0_266_133_66
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
-#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
-#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-/* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE     /* enable fit_format_{error,warning}() */
-
 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
 
 /*
@@ -61,10 +54,6 @@
 /*
  * Commands additional to the ones defined in amcc-common.h
  */
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#undef CONFIG_CMD_EEPROM
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -100,12 +89,27 @@
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0          400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0          0x7F
+#define CONFIG_SYS_I2C_IHS
 
 #define CONFIG_SYS_I2C_SPEED           400000
+#define CONFIG_SYS_SPD_BUS_NUM         4
 
 #define CONFIG_PCA953X                 /* NXP PCA9554 */
 #define CONFIG_PCA9698                 /* NXP PCA9698 */
 
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0             50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0             0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1             50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1             0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2             50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2             0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3             50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3             0x7F
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -122,7 +126,9 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_4            50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4            0x7F
 
-#define CONFIG_SYS_CH7301_I2C                  {1, 2, 3, 4}
+#define CONFIG_SYS_ICS8N3QV01_I2C              {5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C                  {5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C                   {0, 1, 2, 3}
 
 #ifndef __ASSEMBLY__
 void fpga_gpio_set(unsigned int bus, int pin);
@@ -150,12 +156,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
        } while (0)
 #define I2C_DELAY      udelay(25)      /* 1/4 I2C clock duration */
 
-/*
- * OSD hardware
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
-
 /*
  * FLASH organization
  */
@@ -237,10 +237,10 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_OCM_DATA_ADDR       0xF8000000
 #define CONFIG_SYS_OCM_DATA_SIZE       0x1000
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
-#define CONFIG_SYS_INIT_RAM_END        CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
+#define CONFIG_SYS_INIT_RAM_SIZE       CONFIG_SYS_OCM_DATA_SIZE
 
 #define CONFIG_SYS_GBL_DATA_OFFSET \
-       (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
+       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -284,8 +284,9 @@ int fpga_gpio_get(unsigned int bus, int pin);
  * OSD Setup
  */
 #define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
 #define CONFIG_SYS_OSD_SCREENS         1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0     0x01 /* DDR mode 0, DE for H/VSYNC */
 
 #define CONFIG_BITBANGMII              /* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI