#ifndef _CONFIG_KMP204X_H
#define _CONFIG_KMP204X_H
-#define CONFIG_SYS_TEXT_BASE 0xfff40000
-
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
/* an additionnal option is required for UBI as subpage access is
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_BCH
-
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
| BR_PS_8 /* Port Size = 8 bit */ \
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
/* bootcounter in QRIO */
-#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */
-#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
#define CONFIG_SYS_TBIPA_VALUE 8
-#define CONFIG_PHYLIB /* recommended PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC5"
-#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/*
* Environment
/*
* additionnal command line configuration.
*/
-#define CONFIG_CMD_PCI
/* we don't need flash support */
#undef CONFIG_FLASH_CFI_MTD
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
-#ifndef MTDIDS_DEFAULT
-# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand"
-#endif /* MTDIDS_DEFAULT */
-
-#ifndef MTDPARTS_DEFAULT
-# define MTDPARTS_DEFAULT "mtdparts=" \
- "fsl_elbc_nand:" \
- "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
-#endif /* MTDPARTS_DEFAULT */
-
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""