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Merge git://git.denx.de/u-boot-fsl-qoriq
[people/ms/u-boot.git] / include / configs / ls2080aqds.h
diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h
index 145b2572a2237adeb82e814066a6fdc73ead11ca..6b943cdb321ecda82bbc6ee2c554ee67965fe2e7 100644 (file)
--- a/include/configs/ls2080aqds.h
+++ b/include/configs/ls2080aqds.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright 2017 NXP
  * Copyright 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:    GPL-2.0+
@@ -15,7 +16,6 @@ unsigned long get_board_ddr_clk(void);
 #endif
 
 #ifdef CONFIG_FSL_QSPI
-#define CONFIG_SYS_NO_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_QIXIS_I2C_ACCESS
 #define CONFIG_SYS_I2C_EARLY_INIT
@@ -50,7 +50,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_LIBATA
 #define CONFIG_SCSI_AHCI
 #define CONFIG_SCSI_AHCI_PLAT
-#define CONFIG_SCSI
 
 #define CONFIG_SYS_SATA1                       AHCI_BASE_ADDR1
 #define CONFIG_SYS_SATA2                       AHCI_BASE_ADDR2
@@ -59,9 +58,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_SCSI_MAX_LUN                        1
 #define CONFIG_SYS_SCSI_MAX_DEVICE             (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
                                                CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_GPT
 
 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
 
@@ -103,7 +99,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NOR_FTIM3   0x04000000
 #define CONFIG_SYS_IFC_CCR     0x01000000
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
@@ -158,7 +154,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
 
@@ -169,12 +164,14 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_LBMAP_DFLTBANK           0x00
 #define QIXIS_LBMAP_ALTBANK            0x04
 #define QIXIS_LBMAP_NAND               0x09
+#define QIXIS_LBMAP_SD                 0x00
 #define QIXIS_LBMAP_QSPI               0x0f
 #define QIXIS_RST_CTL_RESET            0x31
 #define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
 #define QIXIS_RCFG_CTL_RECONFIG_START  0x21
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_RCW_SRC_NAND             0x107
+#define QIXIS_RCW_SRC_SD               0x40
 #define QIXIS_RCW_SRC_QSPI             0x62
 #define        QIXIS_RST_FORCE_MEM             0x01
 
@@ -201,7 +198,8 @@ unsigned long get_board_ddr_clk(void);
                                        FTIM2_GPCM_TWP(0x3E))
 #define CONFIG_SYS_CS3_FTIM3           0x0
 
-#if defined(CONFIG_SPL) && defined(CONFIG_NAND)
+#if defined(CONFIG_SPL)
+#if defined(CONFIG_NAND_BOOT)
 #define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR0_CSPR_EARLY
 #define CONFIG_SYS_CSPR1_FINAL         CONFIG_SYS_NOR0_CSPR
@@ -230,13 +228,17 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NAND_FTIM3
 
-#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET              (896 * 1024)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x2000
 #define CONFIG_SPL_PAD_TO              0x20000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS    (256 * 1024)
 #define CONFIG_SYS_NAND_U_BOOT_SIZE    (640 * 1024)
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET              0x300000
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_ENV_SIZE                        0x20000
+#endif
 #else
 #define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
 #define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR_EARLY
@@ -266,15 +268,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
 
-#if defined(CONFIG_QSPI_BOOT)
-#define CONFIG_SYS_TEXT_BASE           0x20010000
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SIZE                        0x2000          /* 8KB */
-#define CONFIG_ENV_OFFSET              0x100000        /* 1MB */
-#define CONFIG_ENV_SECT_SIZE           0x10000
-#else
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)
+#ifndef CONFIG_QSPI_BOOT
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x300000)
 #define CONFIG_ENV_SECT_SIZE           0x20000
 #define CONFIG_ENV_SIZE                        0x2000
 #endif
@@ -333,11 +328,9 @@ unsigned long get_board_ddr_clk(void);
 #define RTC
 #define CONFIG_RTC_DS3231               1
 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
-#define CONFIG_CMD_DATE
 
 /* EEPROM */
 #define CONFIG_ID_EEPROM
-#define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_NXID
 #define CONFIG_SYS_EEPROM_BUS_NUM      0
 #define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
@@ -356,7 +349,6 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
 #endif
 
 /* Initial environment variables */
@@ -370,13 +362,30 @@ unsigned long get_board_ddr_clk(void);
        "ramdisk_size=0x2000000\0"              \
        "fdt_high=0xa0000000\0"                 \
        "initrd_high=0xffffffffffffffff\0"      \
-       "kernel_start=0x581100000\0"            \
+       "kernel_start=0x581000000\0"            \
        "kernel_load=0xa0000000\0"              \
        "kernel_size=0x2800000\0"               \
-       "mcinitcmd=esbc_validate 0x580c80000;"  \
-       "esbc_validate 0x580cc0000;"            \
-       "fsl_mc start mc 0x580300000"           \
-       " 0x580800000 \0"
+       "mcmemsize=0x40000000\0"                \
+       "mcinitcmd=esbc_validate 0x580700000;"  \
+       "esbc_validate 0x580740000;"            \
+       "fsl_mc start mc 0x580a00000"           \
+       " 0x580e00000 \0"
+#elif defined(CONFIG_SD_BOOT)
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+       "loadaddr=0x90100000\0"                 \
+       "kernel_addr=0x800\0"                \
+       "ramdisk_addr=0x800000\0"               \
+       "ramdisk_size=0x2000000\0"              \
+       "fdt_high=0xa0000000\0"                 \
+       "initrd_high=0xffffffffffffffff\0"      \
+       "kernel_start=0x8000\0"              \
+       "kernel_load=0xa0000000\0"              \
+       "kernel_size=0x14000\0"               \
+       "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;"  \
+       "mmc read 0x80100000 0x7000 0x800;" \
+       "fsl_mc start mc 0x80000000 0x80100000\0"       \
+       "mcmemsize=0x70000000 \0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS              \
        "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
@@ -386,15 +395,16 @@ unsigned long get_board_ddr_clk(void);
        "ramdisk_size=0x2000000\0"              \
        "fdt_high=0xa0000000\0"                 \
        "initrd_high=0xffffffffffffffff\0"      \
-       "kernel_start=0x581100000\0"            \
+       "kernel_start=0x581000000\0"            \
        "kernel_load=0xa0000000\0"              \
        "kernel_size=0x2800000\0"               \
-       "mcinitcmd=fsl_mc start mc 0x580300000" \
-       " 0x580800000 \0"
+       "mcmemsize=0x40000000\0"                \
+       "mcinitcmd=fsl_mc start mc 0x580a00000" \
+       " 0x580e00000 \0"
 #endif /* CONFIG_SECURE_BOOT */
 
 
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 #define CONFIG_FSL_MEMAC
 #define        CONFIG_PHYLIB
 #define CONFIG_PHYLIB_10G
@@ -435,7 +445,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_HAS_FSL_XHCI_USB
 #define CONFIG_USB_XHCI_FSL
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                2
-#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS     2
 
 #include <asm/fsl_secure_boot.h>
 
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