Convert CONFIG_CMD_EEPROM et al to Kconfig

[people/ms/u-boot.git] / include / configs / p1_p2_rdb_pc.h

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index eb885766d4ab70a8b5c0a2d95ea1ba45c2c100c7..24f751c8392f35ff1ab14e671da11999ee08b9b4 100644 (file)
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -12,7 +12,6 @@
 
 #if defined(CONFIG_TARGET_P1020MBG)
 #define CONFIG_BOARDNAME "P1020MBG-PC"
-#define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0x03
@@ -23,7 +22,6 @@
 
 #if defined(CONFIG_TARGET_P1020UTM)
 #define CONFIG_BOARDNAME "P1020UTM-PC"
-#define CONFIG_P1020
 #define __SW_BOOT_MASK         0x03
 #define __SW_BOOT_NOR          0xe0
 #define __SW_BOOT_SD           0x50
@@ -33,7 +31,6 @@
 #if defined(CONFIG_TARGET_P1020RDB_PC)
 #define CONFIG_BOARDNAME "P1020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0x03
@@ -61,7 +58,6 @@
 #if defined(CONFIG_TARGET_P1020RDB_PD)
 #define CONFIG_BOARDNAME "P1020RDB-PD"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1020
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0x03
@@ -86,7 +82,6 @@
 #if defined(CONFIG_TARGET_P1021RDB)
 #define CONFIG_BOARDNAME "P1021RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1021
 #define CONFIG_QE
 #define CONFIG_VSC7385_ENET
 #define CONFIG_SYS_LBC_LBCR    0x00080000      /* Implement conversion of
@@ -121,7 +116,6 @@
 #if defined(CONFIG_TARGET_P1024RDB)
 #define CONFIG_BOARDNAME "P1024RDB"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1024
 #define CONFIG_SLIC
 #define __SW_BOOT_MASK         0xf3
 #define __SW_BOOT_NOR          0x00
@@ -131,10 +125,9 @@
 #define CONFIG_SYS_L2_SIZE     (256 << 10)
 #endif
 
-#if defined(CONFIG_P1025RDB)
+#if defined(CONFIG_TARGET_P1025RDB)
 #define CONFIG_BOARDNAME "P1025RDB"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P1025
 #define CONFIG_QE
 #define CONFIG_SLIC
 
@@ -148,10 +141,9 @@
 #define CONFIG_SYS_L2_SIZE     (256 << 10)
 #endif
 
-#if defined(CONFIG_P2020RDB)
-#define CONFIG_BOARDNAME "P2020RDB-PCA"
+#if defined(CONFIG_TARGET_P2020RDB)
+#define CONFIG_BOARDNAME "P2020RDB-PC"
 #define CONFIG_NAND_FSL_ELBC
-#define CONFIG_P2020
 #define CONFIG_VSC7385_ENET
 #define __SW_BOOT_MASK         0x03
 #define __SW_BOOT_NOR          0xc8
@@ -182,7 +174,6 @@
 #define CONFIG_SPL_MMC_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW                 /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x11001000
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SPL_PAD_TO              0x20000
@@ -203,7 +194,6 @@
 #define CONFIG_SPL_SPI_FLASH_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET              "u-boot-with-spl.bin"
-#define CONFIG_FSL_LAW         /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE           0x11001000
 #define CONFIG_SPL_TEXT_BASE           0xf8f81000
 #define CONFIG_SPL_PAD_TO              0x20000
@@ -268,13 +258,8 @@
 #endif
 #endif
 
-/* High Level Configuration Options */
-#define CONFIG_BOOKE
-#define CONFIG_E500
-
 #define CONFIG_MP
 
-#define CONFIG_FSL_ELBC
 #define CONFIG_PCIE1   /* PCIE controller 1 (slot 1) */
 #define CONFIG_PCIE2   /* PCIE controller 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT    /* Use common FSL init code */
@@ -282,7 +267,6 @@
 #define CONFIG_FSL_PCIE_RESET  /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT   /* enable 64-bit PCI resources */
 
-#define CONFIG_FSL_LAW
 #define CONFIG_TSEC_ENET       /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 
@@ -292,7 +276,7 @@
 #define CONFIG_LIBATA
 #define CONFIG_LBA48
 
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_SYS_CLK_FREQ    100000000
 #else
 #define CONFIG_SYS_CLK_FREQ    66666666
@@ -306,8 +290,6 @@
 #define CONFIG_L2_CACHE
 #define CONFIG_BTB
 
-#define CONFIG_BOARD_EARLY_INIT_F      /* Call board_pre_init */
-
 #define CONFIG_ENABLE_36BIT_PHYS
 
 #ifdef CONFIG_PHYS_64BIT
@@ -329,7 +311,6 @@
 #endif
 
 /* DDR Setup */
-#define CONFIG_SYS_FSL_DDR3
 #define CONFIG_SYS_DDR_RAW_TIMING
 #define CONFIG_DDR_SPD
 #define CONFIG_SYS_SPD_BUS_NUM 1
@@ -347,11 +328,10 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 
-#define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 
 /* Default settings for DDR3 */
-#ifndef CONFIG_P2020RDB
+#ifndef CONFIG_TARGET_P2020RDB
 #define CONFIG_SYS_DDR_CS0_BNDS                0x0000003f
 #define CONFIG_SYS_DDR_CS0_CONFIG      0x80014302
 #define CONFIG_SYS_DDR_CS0_CONFIG_2    0x00000000
@@ -584,7 +564,7 @@
 #define CONFIG_SPL_RELOC_STACK         (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
 #define CONFIG_SPL_RELOC_STACK_SIZE    (32 << 10)
 #define CONFIG_SPL_RELOC_MALLOC_ADDR   (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
-#if defined(CONFIG_P2020RDB)
+#if defined(CONFIG_TARGET_P2020RDB)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (364 << 10)
 #else
 #define CONFIG_SPL_RELOC_MALLOC_SIZE   (108 << 10)
@@ -651,7 +631,6 @@
 #define CONFIG_SYS_I2C_PCA9557_ADDR    0x18
 
 /* enable read and write access to EEPROM */
-#define CONFIG_CMD_EEPROM
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
@@ -715,7 +694,6 @@
 #define CONFIG_CMD_PCI
 
 #define CONFIG_PCI_SCAN_SHOW   /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
 #endif /* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
@@ -755,7 +733,7 @@
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH   0x10000
 #endif /* CONFIG_QE */
 
-#ifdef CONFIG_P1025RDB
+#ifdef CONFIG_TARGET_P1025RDB
 /*
  * QE UEC ethernet configuration
  */
@@ -789,7 +767,7 @@
 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 #define CONFIG_SYS_UEC5_INTERFACE_SPEED        100
 #endif /* CONFIG_UEC_ETH5 */
-#endif /* CONFIG_P1025RDB */
+#endif /* CONFIG_TARGET_P1025RDB */
 
 /*
  * Environment
@@ -836,7 +814,6 @@
  * Command line configuration.
  */
 #define CONFIG_CMD_IRQ
-#define CONFIG_CMD_DATE
 #define CONFIG_CMD_REGINFO
 
 /*
@@ -845,9 +822,7 @@
 #define CONFIG_HAS_FSL_DR_USB
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_EHCI
-
-#ifdef CONFIG_USB_EHCI
+#ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #define CONFIG_USB_EHCI_FSL
 #endif
@@ -857,17 +832,9 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT        1
 #endif
 
-#define CONFIG_MMC
-
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#define CONFIG_GENERIC_MMC
-#endif
-
-#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
-                || defined(CONFIG_FSL_SATA)
-#define CONFIG_DOS_PARTITION
 #endif
 
 #undef CONFIG_WATCHDOG /* watchdog disabled */
@@ -913,8 +880,6 @@
 
 #define CONFIG_BOOTARGS        /* the boot command will set bootargs */
 
-#define CONFIG_BAUDRATE        115200
-
 #ifdef __SW_BOOT_NOR
 #define __NOR_RST_CMD  \
 norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \